2 * Clock Initialization for board based on EXYNOS4210
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/clk.h>
32 #include <asm/arch/clock.h>
33 #include "common_setup.h"
34 #include "exynos4_setup.h"
37 * system_clock_init: Initialize core clock and bus clock.
38 * void system_clock_init(void)
40 void system_clock_init(void)
42 struct exynos4_clock *clk =
43 (struct exynos4_clock *)samsung_get_base_clock();
45 writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
49 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
50 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
51 writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
52 writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
53 writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
54 writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
55 writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
56 writel(CLK_SRC_CAM_VAL, &clk->src_cam);
57 writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
58 writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
59 writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
63 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
64 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
65 writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
66 writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
67 writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
68 writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
69 writel(CLK_DIV_TOP_VAL, &clk->div_top);
70 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
71 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
72 writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
73 writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
74 writel(CLK_DIV_CAM_VAL, &clk->div_cam);
75 writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
76 writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
77 writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
79 /* Set PLL locktime */
80 writel(PLL_LOCKTIME, &clk->apll_lock);
81 writel(PLL_LOCKTIME, &clk->mpll_lock);
82 writel(PLL_LOCKTIME, &clk->epll_lock);
83 writel(PLL_LOCKTIME, &clk->vpll_lock);
85 writel(APLL_CON1_VAL, &clk->apll_con1);
86 writel(APLL_CON0_VAL, &clk->apll_con0);
87 writel(MPLL_CON1_VAL, &clk->mpll_con1);
88 writel(MPLL_CON0_VAL, &clk->mpll_con0);
89 writel(EPLL_CON1_VAL, &clk->epll_con1);
90 writel(EPLL_CON0_VAL, &clk->epll_con0);
91 writel(VPLL_CON1_VAL, &clk->vpll_con1);
92 writel(VPLL_CON0_VAL, &clk->vpll_con0);