2 * Clock setup for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/clk.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/spl.h>
31 #include <asm/arch/dwmmc.h>
33 #include "clock_init.h"
34 #include "common_setup.h"
35 #include "exynos5_setup.h"
37 #define FSYS1_MMC0_DIV_MASK 0xff0f
38 #define FSYS1_MMC0_DIV_VAL 0x0701
40 DECLARE_GLOBAL_DATA_PTR;
42 struct arm_clk_ratios arm_clk_ratios[] = {
52 .pclk_dbg_ratio = 0x1,
67 .pclk_dbg_ratio = 0x1,
82 .pclk_dbg_ratio = 0x1,
97 .pclk_dbg_ratio = 0x1,
104 .arm_freq_mhz = 1400,
112 .pclk_dbg_ratio = 0x1,
119 .arm_freq_mhz = 1700,
127 .pclk_dbg_ratio = 0x1,
135 struct mem_timings mem_timings[] = {
137 .mem_manuf = MEM_MANUF_ELPIDA,
138 .mem_type = DDR_MODE_DDR3,
139 .frequency_mhz = 800,
159 .pclk_cdrex_ratio = 0x5,
161 0x00020018, 0x00030000, 0x00010042, 0x00000d70
163 .timing_ref = 0x000000bb,
164 .timing_row = 0x8c36650e,
165 .timing_data = 0x3630580b,
166 .timing_power = 0x41000a44,
167 .phy0_dqs = 0x08080808,
168 .phy1_dqs = 0x08080808,
169 .phy0_dq = 0x08080808,
170 .phy1_dq = 0x08080808,
173 .phy0_pulld_dqs = 0xf,
174 .phy1_pulld_dqs = 0xf,
176 .lpddr3_ctrl_phy_reset = 0x1,
177 .ctrl_start_point = 0x10,
199 * Dynamic Clock: Always Running
200 * Memory Burst length: 8
202 * Memory Bus width: 32 bit
204 * Additional Latancy for PLL: 0 Cycle
206 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
207 DMC_MEMCONTROL_DPWRDN_DISABLE |
208 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
209 DMC_MEMCONTROL_TP_DISABLE |
210 DMC_MEMCONTROL_DSREF_ENABLE |
211 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
212 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
213 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
214 DMC_MEMCONTROL_NUM_CHIP_1 |
215 DMC_MEMCONTROL_BL_8 |
216 DMC_MEMCONTROL_PZQ_DISABLE |
217 DMC_MEMCONTROL_MRR_BYTE_7_0,
218 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
219 DMC_MEMCONFIGX_CHIP_COL_10 |
220 DMC_MEMCONFIGX_CHIP_ROW_15 |
221 DMC_MEMCONFIGX_CHIP_BANK_8,
222 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
223 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
224 .prechconfig_tp_cnt = 0xff,
227 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
228 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
229 DMC_CONCONTROL_RD_FETCH_DISABLE |
230 DMC_CONCONTROL_EMPTY_DISABLE |
231 DMC_CONCONTROL_AREF_EN_DISABLE |
232 DMC_CONCONTROL_IO_PD_CON_DISABLE,
234 .chips_per_channel = 2,
235 .chips_to_configure = 1,
237 .impedance = IMP_OUTPUT_DRV_30_OHM,
238 .gate_leveling_enable = 0,
240 .mem_manuf = MEM_MANUF_SAMSUNG,
241 .mem_type = DDR_MODE_DDR3,
242 .frequency_mhz = 800,
262 .pclk_cdrex_ratio = 0x5,
264 0x00020018, 0x00030000, 0x00010000, 0x00000d70
266 .timing_ref = 0x000000bb,
267 .timing_row = 0x8c36650e,
268 .timing_data = 0x3630580b,
269 .timing_power = 0x41000a44,
270 .phy0_dqs = 0x08080808,
271 .phy1_dqs = 0x08080808,
272 .phy0_dq = 0x08080808,
273 .phy1_dq = 0x08080808,
276 .phy0_pulld_dqs = 0xf,
277 .phy1_pulld_dqs = 0xf,
279 .lpddr3_ctrl_phy_reset = 0x1,
280 .ctrl_start_point = 0x10,
302 * Dynamic Clock: Always Running
303 * Memory Burst length: 8
305 * Memory Bus width: 32 bit
307 * Additional Latancy for PLL: 0 Cycle
309 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
310 DMC_MEMCONTROL_DPWRDN_DISABLE |
311 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
312 DMC_MEMCONTROL_TP_DISABLE |
313 DMC_MEMCONTROL_DSREF_ENABLE |
314 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
315 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
316 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
317 DMC_MEMCONTROL_NUM_CHIP_1 |
318 DMC_MEMCONTROL_BL_8 |
319 DMC_MEMCONTROL_PZQ_DISABLE |
320 DMC_MEMCONTROL_MRR_BYTE_7_0,
321 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
322 DMC_MEMCONFIGX_CHIP_COL_10 |
323 DMC_MEMCONFIGX_CHIP_ROW_15 |
324 DMC_MEMCONFIGX_CHIP_BANK_8,
325 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
326 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
327 .prechconfig_tp_cnt = 0xff,
330 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
331 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
332 DMC_CONCONTROL_RD_FETCH_DISABLE |
333 DMC_CONCONTROL_EMPTY_DISABLE |
334 DMC_CONCONTROL_AREF_EN_DISABLE |
335 DMC_CONCONTROL_IO_PD_CON_DISABLE,
337 .chips_per_channel = 2,
338 .chips_to_configure = 1,
340 .impedance = IMP_OUTPUT_DRV_40_OHM,
341 .gate_leveling_enable = 1,
346 * Get the required memory type and speed (SPL version).
348 * In SPL we have no device tree, so we use the machine parameters
350 * @param mem_type Returns memory type
351 * @param frequency_mhz Returns memory speed in MHz
352 * @param arm_freq Returns ARM clock speed in MHz
353 * @param mem_manuf Return Memory Manufacturer name
355 static void clock_get_mem_selection(enum ddr_mode *mem_type,
356 unsigned *frequency_mhz, unsigned *arm_freq,
357 enum mem_manuf *mem_manuf)
359 struct spl_machine_param *params;
361 params = spl_get_machine_params();
362 *mem_type = params->mem_type;
363 *frequency_mhz = params->frequency_mhz;
364 *arm_freq = params->arm_freq_mhz;
365 *mem_manuf = params->mem_manuf;
368 /* Get the ratios for setting ARM clock */
369 struct arm_clk_ratios *get_arm_ratios(void)
371 struct arm_clk_ratios *arm_ratio;
372 enum ddr_mode mem_type;
373 enum mem_manuf mem_manuf;
374 unsigned frequency_mhz, arm_freq;
377 clock_get_mem_selection(&mem_type, &frequency_mhz,
378 &arm_freq, &mem_manuf);
380 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
382 if (arm_ratio->arm_freq_mhz == arm_freq)
386 /* will hang if failed to find clock ratio */
393 struct mem_timings *clock_get_mem_timings(void)
395 struct mem_timings *mem;
396 enum ddr_mode mem_type;
397 enum mem_manuf mem_manuf;
398 unsigned frequency_mhz, arm_freq;
401 clock_get_mem_selection(&mem_type, &frequency_mhz,
402 &arm_freq, &mem_manuf);
403 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
405 if (mem->mem_type == mem_type &&
406 mem->frequency_mhz == frequency_mhz &&
407 mem->mem_manuf == mem_manuf)
411 /* will hang if failed to find memory timings */
418 void system_clock_init()
420 struct exynos5_clock *clk =
421 (struct exynos5_clock *)samsung_get_base_clock();
422 struct mem_timings *mem;
423 struct arm_clk_ratios *arm_clk_ratio;
426 mem = clock_get_mem_timings();
427 arm_clk_ratio = get_arm_ratios();
429 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
431 val = readl(&clk->mux_stat_cpu);
432 } while ((val | MUX_APLL_SEL_MASK) != val);
434 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
436 val = readl(&clk->mux_stat_core1);
437 } while ((val | MUX_MPLL_SEL_MASK) != val);
439 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
440 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
441 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
442 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
443 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
446 val = readl(&clk->mux_stat_top2);
447 } while ((val | tmp) != val);
449 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
451 val = readl(&clk->mux_stat_cdrex);
452 } while ((val | MUX_BPLL_SEL_MASK) != val);
455 writel(APLL_LOCK_VAL, &clk->apll_lock);
457 writel(MPLL_LOCK_VAL, &clk->mpll_lock);
459 writel(BPLL_LOCK_VAL, &clk->bpll_lock);
461 writel(CPLL_LOCK_VAL, &clk->cpll_lock);
463 writel(GPLL_LOCK_VAL, &clk->gpll_lock);
465 writel(EPLL_LOCK_VAL, &clk->epll_lock);
467 writel(VPLL_LOCK_VAL, &clk->vpll_lock);
469 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
471 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
473 val = readl(&clk->mux_stat_cpu);
474 } while ((val | HPM_SEL_SCLK_MPLL) != val);
476 val = arm_clk_ratio->arm2_ratio << 28
477 | arm_clk_ratio->apll_ratio << 24
478 | arm_clk_ratio->pclk_dbg_ratio << 20
479 | arm_clk_ratio->atb_ratio << 16
480 | arm_clk_ratio->periph_ratio << 12
481 | arm_clk_ratio->acp_ratio << 8
482 | arm_clk_ratio->cpud_ratio << 4
483 | arm_clk_ratio->arm_ratio;
484 writel(val, &clk->div_cpu0);
486 val = readl(&clk->div_stat_cpu0);
489 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
491 val = readl(&clk->div_stat_cpu1);
495 writel(APLL_CON1_VAL, &clk->apll_con1);
496 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
497 arm_clk_ratio->apll_sdiv);
498 writel(val, &clk->apll_con0);
499 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
503 writel(MPLL_CON1_VAL, &clk->mpll_con1);
504 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
505 writel(val, &clk->mpll_con0);
506 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
510 writel(BPLL_CON1_VAL, &clk->bpll_con1);
511 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
512 writel(val, &clk->bpll_con0);
513 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
517 writel(CPLL_CON1_VAL, &clk->cpll_con1);
518 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
519 writel(val, &clk->cpll_con0);
520 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
524 writel(GPLL_CON1_VAL, &clk->gpll_con1);
525 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
526 writel(val, &clk->gpll_con0);
527 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
531 writel(EPLL_CON2_VAL, &clk->epll_con2);
532 writel(EPLL_CON1_VAL, &clk->epll_con1);
533 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
534 writel(val, &clk->epll_con0);
535 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
539 writel(VPLL_CON2_VAL, &clk->vpll_con2);
540 writel(VPLL_CON1_VAL, &clk->vpll_con1);
541 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
542 writel(val, &clk->vpll_con0);
543 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
546 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
547 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
548 while (readl(&clk->div_stat_core0) != 0)
551 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
552 while (readl(&clk->div_stat_core1) != 0)
555 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
556 while (readl(&clk->div_stat_sysrgt) != 0)
559 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
560 while (readl(&clk->div_stat_acp) != 0)
563 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
564 while (readl(&clk->div_stat_syslft) != 0)
567 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
568 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
569 writel(TOP2_VAL, &clk->src_top2);
570 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
572 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
573 while (readl(&clk->div_stat_top0))
576 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
577 while (readl(&clk->div_stat_top1))
580 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
582 val = readl(&clk->mux_stat_lex);
583 if (val == (val | 1))
587 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
588 while (readl(&clk->div_stat_lex))
591 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
592 while (readl(&clk->div_stat_r0x))
595 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
596 while (readl(&clk->div_stat_r0x))
599 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
600 while (readl(&clk->div_stat_r1x))
603 writel(CLK_REG_DISABLE, &clk->src_cdrex);
605 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
606 while (readl(&clk->div_stat_cdrex))
609 val = readl(&clk->src_cpu);
610 val |= CLK_SRC_CPU_VAL;
611 writel(val, &clk->src_cpu);
613 val = readl(&clk->src_top2);
614 val |= CLK_SRC_TOP2_VAL;
615 writel(val, &clk->src_top2);
617 val = readl(&clk->src_core1);
618 val |= CLK_SRC_CORE1_VAL;
619 writel(val, &clk->src_core1);
621 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
622 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
623 while (readl(&clk->div_stat_fsys0))
626 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
627 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
628 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
629 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
630 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
631 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
632 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
633 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
635 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
636 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
638 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
639 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
640 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
641 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
643 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
644 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
645 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
646 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
647 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
649 /* FIMD1 SRC CLK SELECTION */
650 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
652 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
653 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
654 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
655 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
656 writel(val, &clk->div_fsys2);
659 void clock_init_dp_clock(void)
661 struct exynos5_clock *clk =
662 (struct exynos5_clock *)samsung_get_base_clock();
664 /* DP clock enable */
665 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
667 /* We run DP at 267 Mhz */
668 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
672 * Set clock divisor value for booting from EMMC.
673 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
675 void emmc_boot_clk_div_set(void)
677 struct exynos5_clock *clk =
678 (struct exynos5_clock *)samsung_get_base_clock();
679 unsigned int div_mmc;
681 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
682 div_mmc |= FSYS1_MMC0_DIV_VAL;
683 writel(div_mmc, (unsigned int) &clk->div_fsys1);