2 * Machine Specific Values for EXYNOS4012 based board
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _ORIGEN_SETUP_H
26 #define _ORIGEN_SETUP_H
30 #include <asm/arch/cpu.h>
32 #ifdef CONFIG_CLK_800_330_165
35 #ifdef CONFIG_CLK_1000_200_200
38 #ifdef CONFIG_CLK_1000_330_165
41 #ifdef CONFIG_CLK_1000_400_200
45 /* Bus Configuration Register Address */
46 #define ASYNC_CONFIG 0x10010350
49 #define MUX_HPM_SEL_MOUTAPLL 0x0
50 #define MUX_HPM_SEL_SCLKMPLL 0x1
51 #define MUX_CORE_SEL_MOUTAPLL 0x0
52 #define MUX_CORE_SEL_SCLKMPLL 0x1
53 #define MUX_MPLL_SEL_FILPLL 0x0
54 #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
55 #define MUX_APLL_SEL_FILPLL 0x0
56 #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
57 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
58 | (MUX_CORE_SEL_MOUTAPLL << 16) \
59 | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
60 | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
63 #define APLL_RATIO 0x0
64 #define PCLK_DBG_RATIO 0x1
66 #define PERIPH_RATIO 0x3
67 #define COREM1_RATIO 0x7
68 #define COREM0_RATIO 0x3
69 #define CORE_RATIO 0x0
70 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
71 | (PCLK_DBG_RATIO << 20) \
73 | (PERIPH_RATIO << 12) \
74 | (COREM1_RATIO << 8) \
75 | (COREM0_RATIO << 4) \
80 #define COPY_RATIO 0x3
81 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
84 #define MUX_PWI_SEL_XXTI 0x0
85 #define MUX_PWI_SEL_XUSBXTI 0x1
86 #define MUX_PWI_SEL_SCLK_HDMI24M 0x2
87 #define MUX_PWI_SEL_SCLK_USBPHY0 0x3
88 #define MUX_PWI_SEL_SCLK_USBPHY1 0x4
89 #define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
90 #define MUX_PWI_SEL_SCLKMPLL 0x6
91 #define MUX_PWI_SEL_SCLKEPLL 0x7
92 #define MUX_PWI_SEL_SCLKVPLL 0x8
93 #define MUX_DPHY_SEL_SCLKMPLL 0x0
94 #define MUX_DPHY_SEL_SCLKAPLL 0x1
95 #define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
96 #define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
97 #define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
98 | (MUX_DPHY_SEL_SCLKMPLL << 8) \
99 | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
102 #define CORE_TIMERS_RATIO 0x1
103 #define COPY2_RATIO 0x3
104 #define DMCP_RATIO 0x1
105 #define DMCD_RATIO 0x1
106 #define DMC_RATIO 0x1
107 #define DPHY_RATIO 0x1
108 #define ACP_PCLK_RATIO 0x1
109 #define ACP_RATIO 0x3
110 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
111 | (COPY2_RATIO << 24) \
112 | (DMCP_RATIO << 20) \
113 | (DMCD_RATIO << 16) \
114 | (DMC_RATIO << 12) \
115 | (DPHY_RATIO << 8) \
116 | (ACP_PCLK_RATIO << 4) \
120 #define DPM_RATIO 0x1
121 #define DVSEM_RATIO 0x1
122 #define PWI_RATIO 0x1
123 #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
124 | (DVSEM_RATIO << 16) \
128 #define MUX_ONENAND_SEL_ACLK_133 0x0
129 #define MUX_ONENAND_SEL_ACLK_160 0x1
130 #define MUX_ACLK_133_SEL_SCLKMPLL 0x0
131 #define MUX_ACLK_133_SEL_SCLKAPLL 0x1
132 #define MUX_ACLK_160_SEL_SCLKMPLL 0x0
133 #define MUX_ACLK_160_SEL_SCLKAPLL 0x1
134 #define MUX_ACLK_100_SEL_SCLKMPLL 0x0
135 #define MUX_ACLK_100_SEL_SCLKAPLL 0x1
136 #define MUX_ACLK_200_SEL_SCLKMPLL 0x0
137 #define MUX_ACLK_200_SEL_SCLKAPLL 0x1
138 #define MUX_VPLL_SEL_FINPLL 0x0
139 #define MUX_VPLL_SEL_FOUTVPLL 0x1
140 #define MUX_EPLL_SEL_FINPLL 0x0
141 #define MUX_EPLL_SEL_FOUTEPLL 0x1
142 #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
143 #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
144 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
145 | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
146 | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
147 | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
148 | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
149 | (MUX_VPLL_SEL_FINPLL << 8) \
150 | (MUX_EPLL_SEL_FINPLL << 4)\
151 | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
154 #define VPLLSRC_SEL_FINPLL 0x0
155 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
156 #define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
159 #define ONENAND_RATIO 0x0
160 #define ACLK_133_RATIO 0x5
161 #define ACLK_160_RATIO 0x4
162 #define ACLK_100_RATIO 0x7
163 #define ACLK_200_RATIO 0x3
164 #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
165 | (ACLK_133_RATIO << 12)\
166 | (ACLK_160_RATIO << 8) \
167 | (ACLK_100_RATIO << 4) \
168 | (ACLK_200_RATIO << 0))
170 /* CLK_SRC_LEFTBUS */
171 #define MUX_GDL_SEL_SCLKMPLL 0x0
172 #define MUX_GDL_SEL_SCLKAPLL 0x1
173 #define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
175 /* CLK_DIV_LEFTBUS */
176 #define GPL_RATIO 0x1
177 #define GDL_RATIO 0x3
178 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
180 /* CLK_SRC_RIGHTBUS */
181 #define MUX_GDR_SEL_SCLKMPLL 0x0
182 #define MUX_GDR_SEL_SCLKAPLL 0x1
183 #define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
185 /* CLK_DIV_RIGHTBUS */
186 #define GPR_RATIO 0x1
187 #define GDR_RATIO 0x3
188 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
190 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
191 #define SATA_SEL_SCLKMPLL 0
192 #define SATA_SEL_SCLKAPLL 1
194 #define MMC_SEL_XXTI 0
195 #define MMC_SEL_XUSBXTI 1
196 #define MMC_SEL_SCLK_HDMI24M 2
197 #define MMC_SEL_SCLK_USBPHY0 3
198 #define MMC_SEL_SCLK_USBPHY1 4
199 #define MMC_SEL_SCLK_HDMIPHY 5
200 #define MMC_SEL_SCLKMPLL 6
201 #define MMC_SEL_SCLKEPLL 7
202 #define MMC_SEL_SCLKVPLL 8
204 #define MMCC0_SEL MMC_SEL_SCLKMPLL
205 #define MMCC1_SEL MMC_SEL_SCLKMPLL
206 #define MMCC2_SEL MMC_SEL_SCLKMPLL
207 #define MMCC3_SEL MMC_SEL_SCLKMPLL
208 #define MMCC4_SEL MMC_SEL_SCLKMPLL
209 #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
210 | (MMCC4_SEL << 16) \
211 | (MMCC3_SEL << 12) \
216 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
218 #define MMC0_RATIO 0xF
219 #define MMC0_PRE_RATIO 0x0
220 #define MMC1_RATIO 0xF
221 #define MMC1_PRE_RATIO 0x0
222 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
223 | (MMC1_RATIO << 16) \
224 | (MMC0_PRE_RATIO << 8) \
228 #define MMC2_RATIO 0xF
229 #define MMC2_PRE_RATIO 0x0
230 #define MMC3_RATIO 0xF
231 #define MMC3_PRE_RATIO 0x0
232 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
233 | (MMC3_RATIO << 16) \
234 | (MMC2_PRE_RATIO << 8) \
238 #define MMC4_RATIO 0xF
239 #define MMC4_PRE_RATIO 0x0
240 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
244 #define UART_SEL_XXTI 0
245 #define UART_SEL_XUSBXTI 1
246 #define UART_SEL_SCLK_HDMI24M 2
247 #define UART_SEL_SCLK_USBPHY0 3
248 #define UART_SEL_SCLK_USBPHY1 4
249 #define UART_SEL_SCLK_HDMIPHY 5
250 #define UART_SEL_SCLKMPLL 6
251 #define UART_SEL_SCLKEPLL 7
252 #define UART_SEL_SCLKVPLL 8
254 #define UART0_SEL UART_SEL_SCLKMPLL
255 #define UART1_SEL UART_SEL_SCLKMPLL
256 #define UART2_SEL UART_SEL_SCLKMPLL
257 #define UART3_SEL UART_SEL_SCLKMPLL
258 #define UART4_SEL UART_SEL_SCLKMPLL
259 #define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
260 | (UART3_SEL << 12) \
265 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
267 #define UART0_RATIO 7
268 #define UART1_RATIO 7
269 #define UART2_RATIO 7
270 #define UART3_RATIO 7
271 #define UART4_RATIO 7
272 #define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
273 | (UART3_RATIO << 12) \
274 | (UART2_RATIO << 8) \
275 | (UART1_RATIO << 4) \
276 | (UART0_RATIO << 0))
278 /* Clock Source CAM/FIMC */
280 #define CAM0_SEL_XUSBXTI 1
281 #define CAM1_SEL_XUSBXTI 1
282 #define CSIS0_SEL_XUSBXTI 1
283 #define CSIS1_SEL_XUSBXTI 1
285 #define FIMC_SEL_SCLKMPLL 6
286 #define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
287 #define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
288 #define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
289 #define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
291 #define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
292 | (CSIS0_SEL_XUSBXTI << 24) \
293 | (CAM1_SEL_XUSBXTI << 20) \
294 | (CAM0_SEL_XUSBXTI << 16) \
295 | (FIMC3_LCLK_SEL << 12) \
296 | (FIMC2_LCLK_SEL << 8) \
297 | (FIMC1_LCLK_SEL << 4) \
298 | (FIMC0_LCLK_SEL << 0))
302 #define FIMC0_LCLK_RATIO 4
303 #define FIMC1_LCLK_RATIO 4
304 #define FIMC2_LCLK_RATIO 4
305 #define FIMC3_LCLK_RATIO 4
306 #define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
307 | (FIMC2_LCLK_RATIO << 8) \
308 | (FIMC1_LCLK_RATIO << 4) \
309 | (FIMC0_LCLK_RATIO << 0))
313 #define MFC_SEL_MPLL 0
315 #define MFC_SEL MOUTMFC_0
316 #define MFC_0_SEL MFC_SEL_MPLL
317 #define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
322 #define CLK_DIV_MFC_VAL (MFC_RATIO)
326 #define G3D_SEL_MPLL 0
328 #define G3D_SEL MOUTG3D_0
329 #define G3D_0_SEL G3D_SEL_MPLL
330 #define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
334 #define CLK_DIV_G3D_VAL (G3D_RATIO)
338 #define FIMD_SEL_SCLKMPLL 6
339 #define MDNIE0_SEL_XUSBXTI 1
340 #define MDNIE_PWM0_SEL_XUSBXTI 1
341 #define MIPI0_SEL_XUSBXTI 1
342 #define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
343 | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
344 | (MDNIE0_SEL_XUSBXTI << 4) \
345 | (FIMD_SEL_SCLKMPLL << 0))
348 #define FIMD0_RATIO 4
349 #define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
351 /* Required period to generate a stable clock output */
353 #define PLL_LOCKTIME 0x1C20
358 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
364 #define APLL_MDIV 0xFA
365 #define APLL_PDIV 0x6
366 #define APLL_SDIV 0x1
367 #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
370 #define APLL_AFC_ENB 0x1
372 #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
375 #define MPLL_MDIV 0xC8
376 #define MPLL_PDIV 0x6
377 #define MPLL_SDIV 0x1
378 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
381 #define MPLL_AFC_ENB 0x0
382 #define MPLL_AFC 0x1C
383 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
386 #define EPLL_MDIV 0x30
387 #define EPLL_PDIV 0x3
388 #define EPLL_SDIV 0x2
389 #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
393 #define EPLL_CON1_VAL (EPLL_K >> 0)
396 #define VPLL_MDIV 0x35
397 #define VPLL_PDIV 0x3
398 #define VPLL_SDIV 0x2
399 #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
402 #define VPLL_SSCG_EN DISABLE
403 #define VPLL_SEL_PF_DN_SPREAD 0x0
404 #define VPLL_MRR 0x11
407 #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
408 | (VPLL_SEL_PF_DN_SPREAD << 29) \
414 #define DIRECT_CMD_NOP 0x07000000
415 #define DIRECT_CMD_ZQ 0x0a000000
416 #define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
417 #define MEM_TIMINGS_MSR_COUNT 4
418 #define CTRL_START (1 << 0)
419 #define CTRL_DLL_ON (1 << 1)
420 #define AREF_EN (1 << 5)
421 #define DRV_TYPE (1 << 6)
424 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
428 unsigned timingpower;
434 unsigned prechconfig;
443 /* MIU Config Register Offsets*/
444 #define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
445 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
446 #define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
447 #define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
448 #define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
449 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
450 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
451 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
452 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
455 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
456 #define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
457 #define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
460 #define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
461 #define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
462 #define INTERLEAVE_ADDR_MAP_EN 0x00000001
464 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
465 /* Interleave_bit0: 0xC*/
466 #define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
468 #ifdef CONFIG_MIU_2BIT_INTERLEAVED
469 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
470 #define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
472 #define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
473 #define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
474 #define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
475 #define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
476 /* Enable SME0 and SME1*/
477 #define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
479 #define FORCE_DLL_RESYNC 3
480 #define DLL_CONTROL_ON 1
482 #define DIRECT_CMD1 0x00020000
483 #define DIRECT_CMD2 0x00030000
484 #define DIRECT_CMD3 0x00010002
485 #define DIRECT_CMD4 0x00000328
487 #define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
488 #define CTRL_ZQ_START (0x1 << 1)
489 #define CTRL_ZQ_DIV (0 << 4)
490 #define CTRL_ZQ_MODE_DDS (0x7 << 8)
491 #define CTRL_ZQ_MODE_TERM (0x2 << 11)
492 #define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
493 #define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
494 #define CTRL_DCC (0xE38 << 20)
495 #define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
496 | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
497 | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
498 | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
500 #define ASYNC (0 << 0)
501 #define CLK_RATIO (1 << 1)
502 #define DIV_PIPE (1 << 3)
503 #define AWR_ON (1 << 4)
504 #define AREF_DISABLE (0 << 5)
505 #define DRV_TYPE_DISABLE (0 << 6)
506 #define CHIP0_NOT_EMPTY (0 << 8)
507 #define CHIP1_NOT_EMPTY (0 << 9)
508 #define DQ_SWAP_DISABLE (0 << 10)
509 #define QOS_FAST_DISABLE (0 << 11)
510 #define RD_FETCH (0x3 << 12)
511 #define TIMEOUT_LEVEL0 (0xFFF << 16)
512 #define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
513 | AREF_DISABLE | DRV_TYPE_DISABLE\
514 | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
515 | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
516 | RD_FETCH | TIMEOUT_LEVEL0)
518 #define CLK_STOP_DISABLE (0 << 1)
519 #define DPWRDN_DISABLE (0 << 2)
520 #define DPWRDN_TYPE (0 << 3)
521 #define TP_DISABLE (0 << 4)
522 #define DSREF_DIABLE (0 << 5)
523 #define ADD_LAT_PALL (1 << 6)
524 #define MEM_TYPE_DDR3 (0x6 << 8)
525 #define MEM_WIDTH_32 (0x2 << 12)
526 #define NUM_CHIP_2 (1 << 16)
527 #define BL_8 (0x3 << 20)
528 #define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
529 | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
530 | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
534 #define CHIP_BANK_8 (0x3 << 0)
535 #define CHIP_ROW_14 (0x2 << 4)
536 #define CHIP_COL_10 (0x3 << 8)
537 #define CHIP_MAP_INTERLEAVED (1 << 12)
538 #define CHIP_MASK (0xe0 << 16)
539 #ifdef CONFIG_MIU_LINEAR
540 #define CHIP0_BASE (0x40 << 24)
541 #define CHIP1_BASE (0x60 << 24)
543 #define CHIP0_BASE (0x20 << 24)
544 #define CHIP1_BASE (0x40 << 24)
546 #define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
547 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
548 #define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
549 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
551 #define TP_CNT (0xff << 24)
552 #define PRECHCONFIG TP_CNT
554 #define CTRL_OFF (0 << 0)
555 #define CTRL_DLL_OFF (0 << 1)
556 #define CTRL_HALF (0 << 2)
557 #define CTRL_DFDQS (1 << 3)
558 #define DQS_DELAY (0 << 4)
559 #define CTRL_START_POINT (0x10 << 8)
560 #define CTRL_INC (0x10 << 16)
561 #define CTRL_FORCE (0x71 << 24)
562 #define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
563 | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
564 | CTRL_INC | CTRL_FORCE)
566 #define CTRL_SHIFTC (0x6 << 0)
567 #define CTRL_REF (8 << 4)
568 #define CTRL_SHGATE (1 << 29)
569 #define TERM_READ_EN (1 << 30)
570 #define TERM_WRITE_EN (1 << 31)
571 #define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
572 | TERM_READ_EN | TERM_WRITE_EN)
574 #define CONTROL2_VAL 0x00000000
577 #define TIMINGREF_VAL 0x000000BB
578 #define TIMINGROW_VAL 0x4046654f
579 #define TIMINGDATA_VAL 0x46400506
580 #define TIMINGPOWER_VAL 0x52000A3C
582 #define TIMINGREF_VAL 0x000000BC
584 #define TIMINGROW_VAL 0x3545548d
585 #define TIMINGDATA_VAL 0x45430506
586 #define TIMINGPOWER_VAL 0x4439033c
589 #define TIMINGROW_VAL 0x45430506
590 #define TIMINGDATA_VAL 0x56500506
591 #define TIMINGPOWER_VAL 0x5444033d