2 * Machine Specific Values for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _SMDK5250_SETUP_H
10 #define _SMDK5250_SETUP_H
13 #include <asm/arch/dmc.h>
16 #define APLL_CON1_VAL (0x00203800)
19 #define MPLL_CON1_VAL (0x00203800)
22 #define CPLL_CON1_VAL (0x00203800)
25 #define GPLL_CON1_VAL (0x00203800)
28 #define EPLL_CON1_VAL 0x00000000
29 #define EPLL_CON2_VAL 0x00000080
32 #define VPLL_CON1_VAL 0x00000000
33 #define VPLL_CON2_VAL 0x00000080
36 #define BPLL_CON1_VAL 0x00203800
39 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
42 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
45 #define MUX_APLL_SEL 1
47 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
48 | (MUX_CPU_SEL << 16) \
51 /* MEMCONTROL register bit fields */
52 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
53 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
54 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
55 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
56 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
57 #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
58 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
60 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
61 #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
62 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
64 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
66 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
67 #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
69 #define DMC_MEMCONTROL_BL_8 (3 << 20)
70 #define DMC_MEMCONTROL_BL_4 (2 << 20)
72 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
74 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
75 #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
76 #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
77 #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
79 /* MEMCONFIG0 register bit fields */
80 #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
81 #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
82 #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
83 #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
84 #define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
86 #define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
87 #define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
88 #define DMC_MEMBASECONFIG_VAL(x) ( \
89 DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
90 DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
93 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
94 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
96 #define DMC_PRECHCONFIG_VAL 0xFF000000
97 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
99 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
100 #define DFI_INIT_START (1 << 28)
101 #define EMPTY (1 << 8)
102 #define AREF_EN (1 << 5)
104 #define DFI_INIT_COMPLETE_CHO (1 << 2)
105 #define DFI_INIT_COMPLETE_CH1 (1 << 3)
107 #define RDLVL_COMPLETE_CHO (1 << 14)
108 #define RDLVL_COMPLETE_CH1 (1 << 15)
110 #define CLK_STOP_EN (1 << 0)
111 #define DPWRDN_EN (1 << 1)
112 #define DSREF_EN (1 << 5)
114 /* COJCONTROL register bit fields */
115 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
116 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
117 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
118 #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
119 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
120 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
121 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
123 /* CLK_DIV_CPU0_VAL */
124 #define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
125 | (APLL_RATIO << 24) \
126 | (PCLK_DBG_RATIO << 20) \
127 | (ATB_RATIO << 16) \
128 | (PERIPH_RATIO << 12) \
130 | (CPUD_RATIO << 4) \
135 #define CLK_SRC_FSYS0_VAL 0x66666
136 #define CLK_DIV_FSYS0_VAL 0x0BB00000
139 #define HPM_RATIO 0x2
140 #define COPY_RATIO 0x0
142 /* CLK_DIV_CPU1 = 0x00000003 */
143 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
147 #define CLK_SRC_CORE0_VAL 0x00000000
150 #define CLK_SRC_CORE1_VAL 0x100
153 #define CLK_DIV_CORE0_VAL 0x00120000
156 #define CLK_DIV_CORE1_VAL 0x07070700
159 #define CLK_DIV_SYSRGT_VAL 0x00000111
162 #define CLK_DIV_ACP_VAL 0x12
165 #define CLK_DIV_SYSLFT_VAL 0x00000311
168 #define CLK_SRC_CDREX_VAL 0x1
171 #define MCLK_CDREX2_RATIO 0x0
172 #define ACLK_EFCON_RATIO 0x1
173 #define MCLK_DPHY_RATIO 0x1
174 #define MCLK_CDREX_RATIO 0x1
175 #define ACLK_C2C_200_RATIO 0x1
176 #define C2C_CLK_400_RATIO 0x1
177 #define PCLK_CDREX_RATIO 0x1
178 #define ACLK_CDREX_RATIO 0x1
180 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
181 | (C2C_CLK_400_RATIO << 6) \
182 | (PCLK_CDREX_RATIO << 4) \
183 | (ACLK_CDREX_RATIO))
186 #define MUX_ACLK_300_GSCL_SEL 0x0
187 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
188 #define MUX_ACLK_400_G3D_MID_SEL 0x0
189 #define MUX_ACLK_333_SEL 0x0
190 #define MUX_ACLK_300_DISP1_SEL 0x0
191 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
192 #define MUX_ACLK_200_SEL 0x0
193 #define MUX_ACLK_166_SEL 0x0
194 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
195 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
196 | (MUX_ACLK_400_G3D_MID_SEL << 20) \
197 | (MUX_ACLK_333_SEL << 16) \
198 | (MUX_ACLK_300_DISP1_SEL << 15) \
199 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
200 | (MUX_ACLK_200_SEL << 12) \
201 | (MUX_ACLK_166_SEL << 8))
204 #define MUX_ACLK_400_G3D_SEL 0x1
205 #define MUX_ACLK_400_ISP_SEL 0x0
206 #define MUX_ACLK_400_IOP_SEL 0x0
207 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
208 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
209 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
210 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
211 |(MUX_ACLK_400_ISP_SEL << 24) \
212 |(MUX_ACLK_400_IOP_SEL << 20) \
213 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
214 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
215 |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
218 #define MUX_GPLL_SEL 0x1
219 #define MUX_BPLL_USER_SEL 0x0
220 #define MUX_MPLL_USER_SEL 0x0
221 #define MUX_VPLL_SEL 0x1
222 #define MUX_EPLL_SEL 0x1
223 #define MUX_CPLL_SEL 0x1
224 #define VPLLSRC_SEL 0x0
225 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
226 | (MUX_BPLL_USER_SEL << 24) \
227 | (MUX_MPLL_USER_SEL << 20) \
228 | (MUX_VPLL_SEL << 16) \
229 | (MUX_EPLL_SEL << 12) \
230 | (MUX_CPLL_SEL << 8) \
233 #define MUX_ACLK_333_SUB_SEL 0x1
234 #define MUX_ACLK_400_SUB_SEL 0x1
235 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
236 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
237 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
238 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
239 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
240 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
241 #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
242 | (MUX_ACLK_400_SUB_SEL << 20) \
243 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
244 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
245 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
246 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
247 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
248 | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
251 #define ACLK_300_DISP1_RATIO 0x2
252 #define ACLK_400_G3D_RATIO 0x0
253 #define ACLK_333_RATIO 0x0
254 #define ACLK_266_RATIO 0x2
255 #define ACLK_200_RATIO 0x3
256 #define ACLK_166_RATIO 0x1
257 #define ACLK_133_RATIO 0x1
258 #define ACLK_66_RATIO 0x5
260 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
261 | (ACLK_400_G3D_RATIO << 24) \
262 | (ACLK_333_RATIO << 20) \
263 | (ACLK_266_RATIO << 16) \
264 | (ACLK_200_RATIO << 12) \
265 | (ACLK_166_RATIO << 8) \
266 | (ACLK_133_RATIO << 4) \
270 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
271 #define ACLK_66_PRE_RATIO 0x1
272 #define ACLK_400_ISP_RATIO 0x1
273 #define ACLK_400_IOP_RATIO 0x1
274 #define ACLK_300_GSCL_RATIO 0x2
276 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
277 | (ACLK_66_PRE_RATIO << 24) \
278 | (ACLK_400_ISP_RATIO << 20) \
279 | (ACLK_400_IOP_RATIO << 16) \
280 | (ACLK_300_GSCL_RATIO << 12))
283 #define APLL_LOCK_VAL (0x546)
285 #define MPLL_LOCK_VAL (0x546)
287 #define CPLL_LOCK_VAL (0x546)
289 #define GPLL_LOCK_VAL (0x546)
291 #define EPLL_LOCK_VAL (0x3A98)
293 #define VPLL_LOCK_VAL (0x3A98)
295 #define BPLL_LOCK_VAL (0x546)
297 #define MUX_APLL_SEL_MASK (1 << 0)
298 #define MUX_MPLL_SEL_MASK (1 << 8)
299 #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
300 #define MUX_CPLL_SEL_MASK (1 << 8)
301 #define MUX_EPLL_SEL_MASK (1 << 12)
302 #define MUX_VPLL_SEL_MASK (1 << 16)
303 #define MUX_GPLL_SEL_MASK (1 << 28)
304 #define MUX_BPLL_SEL_MASK (1 << 0)
305 #define MUX_HPM_SEL_MASK (1 << 20)
306 #define HPM_SEL_SCLK_MPLL (1 << 21)
307 #define APLL_CON0_LOCKED (1 << 29)
308 #define MPLL_CON0_LOCKED (1 << 29)
309 #define BPLL_CON0_LOCKED (1 << 29)
310 #define CPLL_CON0_LOCKED (1 << 29)
311 #define EPLL_CON0_LOCKED (1 << 29)
312 #define GPLL_CON0_LOCKED (1 << 29)
313 #define VPLL_CON0_LOCKED (1 << 29)
314 #define CLK_REG_DISABLE 0x0
315 #define TOP2_VAL 0x0110000
323 /* SRC_CLOCK = SCLK_MPLL */
324 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
325 | (UART3_SEL << 12) \
331 /* SRC_CLOCK = SCLK_MPLL */
335 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
339 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
340 #define SPI0_ISP_SEL 6
341 #define SPI1_ISP_SEL 6
342 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
343 | (SPI0_ISP_SEL << 0)
345 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
346 #define SPI0_ISP_RATIO 0xf
347 #define SPI1_ISP_RATIO 0xf
348 #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
349 | (SPI0_ISP_RATIO << 0)
352 #define UART5_RATIO 7
353 #define UART4_RATIO 7
354 #define UART3_RATIO 7
355 #define UART2_RATIO 7
356 #define UART1_RATIO 7
357 #define UART0_RATIO 7
359 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
360 | (UART2_RATIO << 8) \
361 | (UART1_RATIO << 4) \
364 #define SPI1_RATIO 0x7
365 #define SPI0_RATIO 0xf
366 #define SPI1_SUB_RATIO 0x0
367 #define SPI0_SUB_RATIO 0x0
368 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
369 | ((SPI1_RATIO << 16) \
370 | (SPI0_SUB_RATIO << 8) \
371 | (SPI0_RATIO << 0)))
374 #define SPI2_RATIO 0xf
375 #define SPI2_SUB_RATIO 0x0
376 #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
381 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
384 #define MMC2_RATIO_MASK 0xf
385 #define MMC2_RATIO_VAL 0x3
386 #define MMC2_RATIO_OFFSET 0
388 #define MMC2_PRE_RATIO_MASK 0xff
389 #define MMC2_PRE_RATIO_VAL 0x9
390 #define MMC2_PRE_RATIO_OFFSET 8
392 #define MMC3_RATIO_MASK 0xf
393 #define MMC3_RATIO_VAL 0x1
394 #define MMC3_RATIO_OFFSET 16
396 #define MMC3_PRE_RATIO_MASK 0xff
397 #define MMC3_PRE_RATIO_VAL 0x0
398 #define MMC3_PRE_RATIO_OFFSET 24
401 #define CLK_SRC_LEX_VAL 0x0
404 #define CLK_DIV_LEX_VAL 0x10
407 #define CLK_DIV_R0X_VAL 0x10
410 #define CLK_DIV_R1X_VAL 0x10
413 #define CLK_DIV_ISP0_VAL 0x31
416 #define CLK_DIV_ISP1_VAL 0x0
419 #define CLK_DIV_ISP2_VAL 0x1
421 /* CLK_SRC_DISP1_0 */
422 #define CLK_SRC_DISP1_0_VAL 0x6
426 * For DP, divisor should be 2
428 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
430 /* CLK_GATE_IP_DISP1 */
431 #define CLK_GATE_DP1_ALLOW (1 << 4)
433 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
434 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
436 #define PHY_CON0_RESET_VAL 0x17020a40
437 #define P0_CMD_EN (1 << 14)
438 #define BYTE_RDLVL_EN (1 << 13)
439 #define CTRL_SHGATE (1 << 8)
441 #define PHY_CON1_RESET_VAL 0x09210100
442 #define CTRL_GATEDURADJ_MASK (0xf << 20)
444 #define PHY_CON2_RESET_VAL 0x00010004
445 #define INIT_DESKEW_EN (1 << 6)
446 #define RDLVL_GATE_EN (1 << 24)
448 /*ZQ Configurations */
449 #define PHY_CON16_RESET_VAL 0x08000304
451 #define ZQ_CLK_DIV_EN (1 << 18)
452 #define ZQ_MANUAL_STR (1 << 1)
453 #define ZQ_DONE (1 << 0)
455 #define CTRL_RDLVL_GATE_ENABLE 1
456 #define CTRL_RDLVL_GATE_DISABLE 1
459 #define DIRECT_CMD_NOP 0x07000000
460 #define DIRECT_CMD_PALL 0x01000000
461 #define DIRECT_CMD_ZQINIT 0x0a000000
462 #define DIRECT_CMD_CHANNEL_SHIFT 28
463 #define DIRECT_CMD_CHIP_SHIFT 20
465 /* DMC PHY Control0 register */
466 #define PHY_CONTROL0_RESET_VAL 0x0
467 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
468 #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
469 #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
470 #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
472 /* Driver strength for CK, CKE, CS & CA */
473 #define IMP_OUTPUT_DRV_40_OHM 0x5
474 #define IMP_OUTPUT_DRV_30_OHM 0x7
475 #define CA_CK_DRVR_DS_OFFSET 9
476 #define CA_CKE_DRVR_DS_OFFSET 6
477 #define CA_CS_DRVR_DS_OFFSET 3
478 #define CA_ADR_DRVR_DS_OFFSET 0
480 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
481 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
485 /* Errors that we can encourter in low-level setup */
488 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
489 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
493 * Memory variant specific initialization code
495 * @param mem Memory timings for this memory type.
496 * @param mem_iv_size Memory interleaving size is a configurable parameter
497 * which the DMC uses to decide how to split a memory
498 * chunk into smaller chunks to support concurrent
499 * accesses; may vary across boards.
500 * @param reset Reset DDR PHY during initialization.
501 * @return 0 if ok, SETUP_ERR_... if there is a problem
503 int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
507 * Configure ZQ I/O interface
509 * @param mem Memory timings for this memory type.
510 * @param phy0_ctrl Pointer to struct containing PHY0 control reg
511 * @param phy1_ctrl Pointer to struct containing PHY1 control reg
512 * @return 0 if ok, -1 on error
514 int dmc_config_zq(struct mem_timings *mem,
515 struct exynos5_phy_control *phy0_ctrl,
516 struct exynos5_phy_control *phy1_ctrl);
519 * Send NOP and MRS/EMRS Direct commands
521 * @param mem Memory timings for this memory type.
522 * @param dmc Pointer to struct of DMC registers
524 void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
527 * Send PALL Direct commands
529 * @param mem Memory timings for this memory type.
530 * @param dmc Pointer to struct of DMC registers
532 void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
535 * Configure the memconfig and membaseconfig registers
537 * @param mem Memory timings for this memory type.
538 * @param exynos5_dmc Pointer to struct of DMC registers
540 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
543 * Reset the DLL. This function is common between DDR3 and LPDDR2.
544 * However, the reset value is different. So we are passing a flag
545 * ddr_mode to distinguish between LPDDR2 and DDR3.
547 * @param exynos5_dmc Pointer to struct of DMC registers
548 * @param ddr_mode Type of DDR memory
550 void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);