2 * Machine Specific Values for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _SMDK5250_SETUP_H
10 #define _SMDK5250_SETUP_H
13 #include <asm/arch/dmc.h>
15 #define NOT_AVAILABLE 0
16 #define DATA_MASK 0xFFFFF
18 #define ENABLE_BIT 0x1
19 #define DISABLE_BIT 0x0
20 #define CA_SWAP_EN (1 << 0)
23 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
25 /* MEMCONTROL register bit fields */
26 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
27 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
28 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
29 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
30 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
31 #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
32 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
34 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
35 #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
36 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
38 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
40 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
41 #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
43 #define DMC_MEMCONTROL_BL_8 (3 << 20)
44 #define DMC_MEMCONTROL_BL_4 (2 << 20)
46 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
48 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
49 #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
50 #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
51 #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
53 /* MEMCONFIG0 register bit fields */
54 #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
55 #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
56 #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
57 #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
58 #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
59 #define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
61 #define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
62 #define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
63 #define DMC_MEMBASECONFIG_VAL(x) ( \
64 DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
65 DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
69 * As we use channel interleaving, therefore value of the base address
70 * register must be set as half of the bus base address
71 * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
72 * we need to set half 0x10 to the membaseconfigx registers
73 * see exynos5420 UM section 17.17.3.21 for more.
75 #define DMC_CHIP_BASE_0 0x10
76 #define DMC_CHIP_BASE_1 0x50
77 #define DMC_CHIP_MASK 0x7C0
79 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
80 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
82 #define DMC_PRECHCONFIG_VAL 0xFF000000
83 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
85 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
86 #define DFI_INIT_START (1 << 28)
87 #define EMPTY (1 << 8)
88 #define AREF_EN (1 << 5)
90 #define DFI_INIT_COMPLETE_CHO (1 << 2)
91 #define DFI_INIT_COMPLETE_CH1 (1 << 3)
93 #define RDLVL_COMPLETE_CHO (1 << 14)
94 #define RDLVL_COMPLETE_CH1 (1 << 15)
96 #define CLK_STOP_EN (1 << 0)
97 #define DPWRDN_EN (1 << 1)
98 #define DSREF_EN (1 << 5)
100 /* COJCONTROL register bit fields */
101 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
102 #define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
103 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
104 #define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
105 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
106 #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
107 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
108 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
109 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
111 #define DMC_CONCONTROL_VAL 0x1FFF2101
113 #define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
114 | DMC_CONCONTROL_AREF_EN_ENABLE \
115 | DMC_CONCONTROL_IO_PD_CON_ENABLE
117 #define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
120 #define HPM_RATIO 0x2
121 #define COPY_RATIO 0x0
123 /* CLK_DIV_CPU1 = 0x00000003 */
124 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
128 #define CLK_SRC_CORE0_VAL 0x00000000
131 #define CLK_SRC_CORE1_VAL 0x100
134 #define CLK_DIV_CORE0_VAL 0x00120000
137 #define CLK_DIV_CORE1_VAL 0x07070700
140 #define CLK_DIV_SYSRGT_VAL 0x00000111
143 #define CLK_DIV_ACP_VAL 0x12
146 #define CLK_DIV_SYSLFT_VAL 0x00000311
148 #define MUX_APLL_SEL_MASK (1 << 0)
149 #define MUX_MPLL_SEL_MASK (1 << 8)
150 #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
151 #define MUX_CPLL_SEL_MASK (1 << 8)
152 #define MUX_EPLL_SEL_MASK (1 << 12)
153 #define MUX_VPLL_SEL_MASK (1 << 16)
154 #define MUX_GPLL_SEL_MASK (1 << 28)
155 #define MUX_BPLL_SEL_MASK (1 << 0)
156 #define MUX_HPM_SEL_MASK (1 << 20)
157 #define HPM_SEL_SCLK_MPLL (1 << 21)
158 #define PLL_LOCKED (1 << 29)
159 #define APLL_CON0_LOCKED (1 << 29)
160 #define MPLL_CON0_LOCKED (1 << 29)
161 #define BPLL_CON0_LOCKED (1 << 29)
162 #define CPLL_CON0_LOCKED (1 << 29)
163 #define EPLL_CON0_LOCKED (1 << 29)
164 #define GPLL_CON0_LOCKED (1 << 29)
165 #define VPLL_CON0_LOCKED (1 << 29)
166 #define CLK_REG_DISABLE 0x0
167 #define TOP2_VAL 0x0110000
169 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
170 #define SPI0_ISP_SEL 6
171 #define SPI1_ISP_SEL 6
172 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
173 | (SPI0_ISP_SEL << 0)
175 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
176 #define SPI0_ISP_RATIO 0xf
177 #define SPI1_ISP_RATIO 0xf
178 #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
179 | (SPI0_ISP_RATIO << 0)
182 #define MMC2_RATIO_MASK 0xf
183 #define MMC2_RATIO_VAL 0x3
184 #define MMC2_RATIO_OFFSET 0
186 #define MMC2_PRE_RATIO_MASK 0xff
187 #define MMC2_PRE_RATIO_VAL 0x9
188 #define MMC2_PRE_RATIO_OFFSET 8
190 #define MMC3_RATIO_MASK 0xf
191 #define MMC3_RATIO_VAL 0x1
192 #define MMC3_RATIO_OFFSET 16
194 #define MMC3_PRE_RATIO_MASK 0xff
195 #define MMC3_PRE_RATIO_VAL 0x0
196 #define MMC3_PRE_RATIO_OFFSET 24
199 #define CLK_SRC_LEX_VAL 0x0
202 #define CLK_DIV_LEX_VAL 0x10
205 #define CLK_DIV_R0X_VAL 0x10
208 #define CLK_DIV_R1X_VAL 0x10
211 #define CLK_DIV_ISP2_VAL 0x1
214 #define SRC_KFC_HPM_SEL (1 << 15)
217 #define CLK_SRC_KFC_VAL 0x00008001
220 #define CLK_DIV_KFC_VAL 0x03300110
223 #define CLK_DIV2_RATIO 0x10111150
226 #define CLK_DIV4_RATIO 0x00000003
229 #define CLK_DIV_G2D 0x00000010
233 * For DP, divisor should be 2
235 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
237 /* CLK_GATE_IP_DISP1 */
238 #define CLK_GATE_DP1_ALLOW (1 << 4)
241 #define AUDIO0_SEL_EPLL (0x6 << 28)
242 #define AUDIO0_RATIO 0x5
243 #define PCM0_RATIO 0x3
244 #define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
247 #define MUX_MCLK_CDR_MSPLL (1 << 4)
248 #define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
249 #define BPLL_SEL_MASK 0x7
252 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
253 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
255 #define PHY_CON0_RESET_VAL 0x17020a40
256 #define P0_CMD_EN (1 << 14)
257 #define BYTE_RDLVL_EN (1 << 13)
258 #define CTRL_SHGATE (1 << 8)
260 #define PHY_CON1_RESET_VAL 0x09210100
261 #define RDLVL_PASS_ADJ_VAL 0x6
262 #define RDLVL_PASS_ADJ_OFFSET 16
263 #define CTRL_GATEDURADJ_MASK (0xf << 20)
264 #define READ_LEVELLING_DDR3 0x0100
266 #define PHY_CON2_RESET_VAL 0x00010004
267 #define INIT_DESKEW_EN (1 << 6)
268 #define DLL_DESKEW_EN (1 << 12)
269 #define RDLVL_GATE_EN (1 << 24)
270 #define RDLVL_EN (1 << 25)
271 #define RDLVL_INCR_ADJ (0x1 << 16)
274 #define DREX_PAUSE_EN (1 << 0)
276 #define BYPASS_EN (1 << 22)
279 #define PHY_CON0_VAL 0x17021A00
281 #define PHY_CON12_RESET_VAL 0x10100070
282 #define PHY_CON12_VAL 0x10107F50
283 #define CTRL_START (1 << 6)
284 #define CTRL_DLL_ON (1 << 5)
285 #define CTRL_LOCK_COARSE_OFFSET 10
286 #define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
287 #define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
288 CTRL_LOCK_COARSE_OFFSET)
289 #define CTRL_FORCE_MASK (0x7F << 8)
290 #define CTRL_FINE_LOCKED 0x7
292 #define CTRL_OFFSETD_RESET_VAL 0x8
293 #define CTRL_OFFSETD_VAL 0x7F
295 #define CTRL_OFFSETR0 0x7F
296 #define CTRL_OFFSETR1 0x7F
297 #define CTRL_OFFSETR2 0x7F
298 #define CTRL_OFFSETR3 0x7F
299 #define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
300 CTRL_OFFSETR1 << 8 | \
301 CTRL_OFFSETR2 << 16 | \
303 #define PHY_CON4_RESET_VAL 0x08080808
305 #define CTRL_OFFSETW0 0x7F
306 #define CTRL_OFFSETW1 0x7F
307 #define CTRL_OFFSETW2 0x7F
308 #define CTRL_OFFSETW3 0x7F
309 #define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
310 CTRL_OFFSETW1 << 8 | \
311 CTRL_OFFSETW2 << 16 | \
313 #define PHY_CON6_RESET_VAL 0x08080808
315 #define PHY_CON14_RESET_VAL 0x001F0000
316 #define CTRL_PULLD_DQS 0xF
317 #define CTRL_PULLD_DQS_OFFSET 0
319 /* ZQ Configurations */
320 #define PHY_CON16_RESET_VAL 0x08000304
322 #define ZQ_CLK_EN (1 << 27)
323 #define ZQ_CLK_DIV_EN (1 << 18)
324 #define ZQ_MANUAL_STR (1 << 1)
325 #define ZQ_DONE (1 << 0)
326 #define ZQ_MODE_DDS_OFFSET 24
328 #define CTRL_RDLVL_GATE_ENABLE 1
329 #define CTRL_RDLVL_GATE_DISABLE 0
330 #define CTRL_RDLVL_DATA_ENABLE 2
333 #define DIRECT_CMD_NOP 0x07000000
334 #define DIRECT_CMD_PALL 0x01000000
335 #define DIRECT_CMD_ZQINIT 0x0a000000
336 #define DIRECT_CMD_CHANNEL_SHIFT 28
337 #define DIRECT_CMD_CHIP_SHIFT 20
338 #define DIRECT_CMD_BANK_SHIFT 16
339 #define DIRECT_CMD_REFA (5 << 24)
340 #define DIRECT_CMD_MRS1 0x71C00
341 #define DIRECT_CMD_MRS2 0x10BFC
342 #define DIRECT_CMD_MRS3 0x0050C
343 #define DIRECT_CMD_MRS4 0x00868
344 #define DIRECT_CMD_MRS5 0x00C04
347 #define IMPEDANCE_48_OHM 4
348 #define IMPEDANCE_40_OHM 5
349 #define IMPEDANCE_34_OHM 6
350 #define IMPEDANCE_30_OHM 7
351 #define PHY_CON39_VAL_48_OHM 0x09240924
352 #define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
353 #define PHY_CON39_VAL_34_OHM 0x0DB60DB6
354 #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
356 #define CTRL_BSTLEN_OFFSET 8
357 #define CTRL_RDLAT_OFFSET 0
359 #define CMD_DEFAULT_LPDDR3 0xF
360 #define CMD_DEFUALT_OFFSET 0
361 #define T_WRDATA_EN 0x7
362 #define T_WRDATA_EN_DDR3 0x8
363 #define T_WRDATA_EN_OFFSET 16
364 #define T_WRDATA_EN_MASK 0x1f
366 #define PHY_CON31_VAL 0x0C183060
367 #define PHY_CON32_VAL 0x60C18306
368 #define PHY_CON33_VAL 0x00000030
370 #define PHY_CON31_RESET_VAL 0x0
371 #define PHY_CON32_RESET_VAL 0x0
372 #define PHY_CON33_RESET_VAL 0x0
374 #define SL_DLL_DYN_CON_EN (1 << 1)
375 #define FP_RESYNC (1 << 3)
376 #define CTRL_START (1 << 6)
378 #define DMC_AREF_EN (1 << 5)
379 #define DMC_CONCONTROL_EMPTY (1 << 8)
380 #define DFI_INIT_START (1 << 28)
382 #define DMC_MEMCONTROL_VAL 0x00312700
383 #define CLK_STOP_EN (1 << 0)
384 #define DPWRDN_EN (1 << 1)
385 #define DSREF_EN (1 << 5)
387 #define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
388 #define MEMBASECONFIG_CHIP_MASK_OFFSET 0
389 #define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
390 #define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
391 #define CHIP_BASE_OFFSET 16
393 #define MEMCONFIG_VAL 0x1323
394 #define PRECHCONFIG_DEFAULT_VAL 0xFF000000
395 #define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
397 #define TIMINGAREF_VAL 0x5d
398 #define TIMINGROW_VAL 0x345A8692
399 #define TIMINGDATA_VAL 0x3630065C
400 #define TIMINGPOWER_VAL 0x50380336
401 #define DFI_INIT_COMPLETE (1 << 3)
403 #define BRBRSVCONTROL_VAL 0x00000033
404 #define BRBRSVCONFIG_VAL 0x88778877
406 /* Clock Gating Control (CGCONTROL) register */
407 #define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
408 #define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
409 #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
410 #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
411 #define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
412 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
414 /* DMC PHY Control0 register */
415 #define PHY_CONTROL0_RESET_VAL 0x0
416 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
417 #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
418 #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
419 #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
421 /* Driver strength for CK, CKE, CS & CA */
422 #define IMP_OUTPUT_DRV_40_OHM 0x5
423 #define IMP_OUTPUT_DRV_30_OHM 0x7
424 #define DA_3_DS_OFFSET 25
425 #define DA_2_DS_OFFSET 22
426 #define DA_1_DS_OFFSET 19
427 #define DA_0_DS_OFFSET 16
428 #define CA_CK_DRVR_DS_OFFSET 9
429 #define CA_CKE_DRVR_DS_OFFSET 6
430 #define CA_CS_DRVR_DS_OFFSET 3
431 #define CA_ADR_DRVR_DS_OFFSET 0
433 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
434 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
437 * Definitions that differ with SoC's.
438 * Below is the part defining macros for Exynos5250.
439 * Else part introduces macros for Exynos5420.
441 #ifndef CONFIG_EXYNOS5420
444 #define APLL_CON1_VAL (0x00203800)
447 #define MPLL_CON1_VAL (0x00203800)
450 #define CPLL_CON1_VAL (0x00203800)
453 #define DPLL_CON1_VAL (NOT_AVAILABLE)
456 #define GPLL_CON1_VAL (0x00203800)
458 /* EPLL_CON1, CON2 */
459 #define EPLL_CON1_VAL 0x00000000
460 #define EPLL_CON2_VAL 0x00000080
462 /* VPLL_CON1, CON2 */
463 #define VPLL_CON1_VAL 0x00000000
464 #define VPLL_CON2_VAL 0x00000080
466 /* RPLL_CON1, CON2 */
467 #define RPLL_CON1_VAL NOT_AVAILABLE
468 #define RPLL_CON2_VAL NOT_AVAILABLE
471 #define BPLL_CON1_VAL 0x00203800
474 #define SPLL_CON1_VAL NOT_AVAILABLE
477 #define IPLL_CON1_VAL NOT_AVAILABLE
480 #define KPLL_CON1_VAL NOT_AVAILABLE
483 #define CLK_SRC_ISP_VAL NOT_AVAILABLE
484 #define CLK_DIV_ISP0_VAL 0x31
485 #define CLK_DIV_ISP1_VAL 0x0
488 #define CLK_SRC_FSYS0_VAL 0x66666
489 #define CLK_DIV_FSYS0_VAL 0x0BB00000
490 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
491 #define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
494 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
495 #define MUX_HPM_SEL 0
496 #define MUX_CPU_SEL 0
497 #define MUX_APLL_SEL 1
499 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
500 | (MUX_CPU_SEL << 16) \
504 #define CLK_SRC_CDREX_VAL 0x1
507 #define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
508 #define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
510 /* CLK_DIV_CPU0_VAL */
511 #define CLK_DIV_CPU0_VAL NOT_AVAILABLE
513 #define MCLK_CDREX2_RATIO 0x0
514 #define ACLK_EFCON_RATIO 0x1
515 #define MCLK_DPHY_RATIO 0x1
516 #define MCLK_CDREX_RATIO 0x1
517 #define ACLK_C2C_200_RATIO 0x1
518 #define C2C_CLK_400_RATIO 0x1
519 #define PCLK_CDREX_RATIO 0x1
520 #define ACLK_CDREX_RATIO 0x1
522 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
523 | (C2C_CLK_400_RATIO << 6) \
524 | (PCLK_CDREX_RATIO << 4) \
525 | (ACLK_CDREX_RATIO))
528 #define MUX_ACLK_300_GSCL_SEL 0x0
529 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
530 #define MUX_ACLK_400_G3D_MID_SEL 0x0
531 #define MUX_ACLK_333_SEL 0x0
532 #define MUX_ACLK_300_DISP1_SEL 0x0
533 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
534 #define MUX_ACLK_200_SEL 0x0
535 #define MUX_ACLK_166_SEL 0x0
536 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
537 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
538 | (MUX_ACLK_400_G3D_MID_SEL << 20) \
539 | (MUX_ACLK_333_SEL << 16) \
540 | (MUX_ACLK_300_DISP1_SEL << 15) \
541 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
542 | (MUX_ACLK_200_SEL << 12) \
543 | (MUX_ACLK_166_SEL << 8))
546 #define MUX_ACLK_400_G3D_SEL 0x1
547 #define MUX_ACLK_400_ISP_SEL 0x0
548 #define MUX_ACLK_400_IOP_SEL 0x0
549 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
550 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
551 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
552 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
553 |(MUX_ACLK_400_ISP_SEL << 24) \
554 |(MUX_ACLK_400_IOP_SEL << 20) \
555 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
556 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
557 |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
560 #define MUX_GPLL_SEL 0x1
561 #define MUX_BPLL_USER_SEL 0x0
562 #define MUX_MPLL_USER_SEL 0x0
563 #define MUX_VPLL_SEL 0x1
564 #define MUX_EPLL_SEL 0x1
565 #define MUX_CPLL_SEL 0x1
566 #define VPLLSRC_SEL 0x0
567 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
568 | (MUX_BPLL_USER_SEL << 24) \
569 | (MUX_MPLL_USER_SEL << 20) \
570 | (MUX_VPLL_SEL << 16) \
571 | (MUX_EPLL_SEL << 12) \
572 | (MUX_CPLL_SEL << 8) \
575 #define MUX_ACLK_333_SUB_SEL 0x1
576 #define MUX_ACLK_400_SUB_SEL 0x1
577 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
578 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
579 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
580 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
581 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
582 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
583 #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
584 | (MUX_ACLK_400_SUB_SEL << 20) \
585 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
586 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
587 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
588 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
589 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
590 | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
592 #define CLK_SRC_TOP4_VAL NOT_AVAILABLE
593 #define CLK_SRC_TOP5_VAL NOT_AVAILABLE
594 #define CLK_SRC_TOP6_VAL NOT_AVAILABLE
595 #define CLK_SRC_TOP7_VAL NOT_AVAILABLE
598 #define ACLK_300_DISP1_RATIO 0x2
599 #define ACLK_400_G3D_RATIO 0x0
600 #define ACLK_333_RATIO 0x0
601 #define ACLK_266_RATIO 0x2
602 #define ACLK_200_RATIO 0x3
603 #define ACLK_166_RATIO 0x1
604 #define ACLK_133_RATIO 0x1
605 #define ACLK_66_RATIO 0x5
607 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
608 | (ACLK_400_G3D_RATIO << 24) \
609 | (ACLK_333_RATIO << 20) \
610 | (ACLK_266_RATIO << 16) \
611 | (ACLK_200_RATIO << 12) \
612 | (ACLK_166_RATIO << 8) \
613 | (ACLK_133_RATIO << 4) \
617 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
618 #define ACLK_66_PRE_RATIO 0x1
619 #define ACLK_400_ISP_RATIO 0x1
620 #define ACLK_400_IOP_RATIO 0x1
621 #define ACLK_300_GSCL_RATIO 0x2
623 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
624 | (ACLK_66_PRE_RATIO << 24) \
625 | (ACLK_400_ISP_RATIO << 20) \
626 | (ACLK_400_IOP_RATIO << 16) \
627 | (ACLK_300_GSCL_RATIO << 12))
629 #define CLK_DIV_TOP2_VAL NOT_AVAILABLE
631 /* PLL Lock Value Factor */
632 #define PLL_LOCK_FACTOR 250
633 #define PLL_X_LOCK_FACTOR 3000
641 /* SRC_CLOCK = SCLK_MPLL */
642 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
643 | (UART3_SEL << 12) \
649 /* SRC_CLOCK = SCLK_MPLL */
653 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
658 #define UART5_RATIO 7
659 #define UART4_RATIO 7
660 #define UART3_RATIO 7
661 #define UART2_RATIO 7
662 #define UART1_RATIO 7
663 #define UART0_RATIO 7
665 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
666 | (UART2_RATIO << 8) \
667 | (UART1_RATIO << 4) \
670 #define SPI1_RATIO 0x7
671 #define SPI0_RATIO 0xf
672 #define SPI1_SUB_RATIO 0x0
673 #define SPI0_SUB_RATIO 0x0
674 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
675 | ((SPI1_RATIO << 16) \
676 | (SPI0_SUB_RATIO << 8) \
677 | (SPI0_RATIO << 0)))
680 #define SPI2_RATIO 0xf
681 #define SPI2_SUB_RATIO 0x0
682 #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
687 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
691 #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
693 /* CLK_SRC_DISP1_0 */
694 #define CLK_SRC_DISP1_0_VAL 0x6
695 #define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
697 #define APLL_FOUT (1 << 0)
698 #define KPLL_FOUT NOT_AVAILABLE
700 #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
703 #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
706 #define APLL_CON1_VAL (0x0020F300)
709 #define MPLL_CON1_VAL (0x0020F300)
713 #define CPLL_CON1_VAL 0x0020f300
716 #define DPLL_CON1_VAL (0x0020F300)
719 #define GPLL_CON1_VAL (NOT_AVAILABLE)
722 /* EPLL_CON1, CON2 */
723 #define EPLL_CON1_VAL 0x00000000
724 #define EPLL_CON2_VAL 0x00000080
726 /* VPLL_CON1, CON2 */
727 #define VPLL_CON1_VAL 0x0020f300
728 #define VPLL_CON2_VAL NOT_AVAILABLE
730 /* RPLL_CON1, CON2 */
731 #define RPLL_CON1_VAL 0x00000000
732 #define RPLL_CON2_VAL 0x00000080
735 #define BPLL_CON1_VAL 0x0020f300
738 #define SPLL_CON1_VAL 0x0020f300
741 #define IPLL_CON1_VAL 0x00000080
744 #define KPLL_CON1_VAL 0x200000
747 #define CLK_SRC_ISP_VAL 0x33366000
748 #define CLK_DIV_ISP0_VAL 0x13131300
749 #define CLK_DIV_ISP1_VAL 0xbb110202
753 #define CLK_SRC_FSYS0_VAL 0x33033300
754 #define CLK_DIV_FSYS0_VAL 0x0
755 #define CLK_DIV_FSYS1_VAL 0x04f13c4f
756 #define CLK_DIV_FSYS2_VAL 0x041d0000
759 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
760 #define MUX_HPM_SEL 1
761 #define MUX_CPU_SEL 0
762 #define MUX_APLL_SEL 1
764 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
765 | (MUX_CPU_SEL << 16) \
769 #define CLK_SRC_CDREX_VAL 0x00000011
772 #define CLK_DIV_CDREX0_VAL 0x30010100
773 #define CLK_DIV_CDREX1_VAL 0x300
775 #define CLK_DIV_CDREX_VAL 0x17010100
777 /* CLK_DIV_CPU0_VAL */
778 #define CLK_DIV_CPU0_VAL 0x01440020
781 #define CLK_SRC_TOP0_VAL 0x12221222
782 #define CLK_SRC_TOP1_VAL 0x00100200
783 #define CLK_SRC_TOP2_VAL 0x11101000
784 #define CLK_SRC_TOP3_VAL 0x11111111
785 #define CLK_SRC_TOP4_VAL 0x11110111
786 #define CLK_SRC_TOP5_VAL 0x11111101
787 #define CLK_SRC_TOP6_VAL 0x11110111
788 #define CLK_SRC_TOP7_VAL 0x00022200
791 #define CLK_DIV_TOP0_VAL 0x23712311
792 #define CLK_DIV_TOP1_VAL 0x13100B00
793 #define CLK_DIV_TOP2_VAL 0x11101100
795 /* PLL Lock Value Factor */
796 #define PLL_LOCK_FACTOR 200
797 #define PLL_X_LOCK_FACTOR 3000
807 /* SRC_CLOCK = SCLK_RPLL */
808 #define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
810 | (UART4_SEL << 20) \
811 | (UART3_SEL << 16) \
812 | (UART2_SEL << 12) \
817 /* SRC_CLOCK = SCLK_EPLL */
824 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
827 | (AUDIO2_SEL << 16) \
828 | (AUDIO2_SEL << 12) \
833 #define UART4_RATIO 9
834 #define UART3_RATIO 9
835 #define UART2_RATIO 9
836 #define UART1_RATIO 9
837 #define UART0_RATIO 9
839 #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
840 | (UART4_RATIO << 24) \
841 | (UART3_RATIO << 20) \
842 | (UART2_RATIO << 16) \
843 | (UART1_RATIO << 12) \
844 | (UART0_RATIO << 8))
846 #define SPI2_RATIO 0x1
847 #define SPI1_RATIO 0x1
848 #define SPI0_RATIO 0x1
849 #define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
850 | (SPI1_RATIO << 24) \
851 | (SPI0_RATIO << 20))
854 #define PCM2_RATIO 0x3
855 #define PCM1_RATIO 0x3
856 #define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
857 | (PCM1_RATIO << 16))
860 #define AUDIO2_RATIO 0x5
861 #define AUDIO1_RATIO 0x5
862 #define AUDIO0_RATIO 0x5
863 #define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
864 | (AUDIO1_RATIO << 24) \
865 | (AUDIO0_RATIO << 20))
868 #define SPI2_PRE_RATIO 0x2
869 #define SPI1_PRE_RATIO 0x2
870 #define SPI0_PRE_RATIO 0x2
871 #define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
872 | (SPI1_PRE_RATIO << 16) \
873 | (SPI0_PRE_RATIO << 8))
875 /* CLK_SRC_DISP1_0 */
876 #define CLK_SRC_DISP1_0_VAL 0x10666600
877 #define CLK_DIV_DISP1_0_VAL 0x01050211
879 #define APLL_FOUT (1 << 0)
880 #define KPLL_FOUT (1 << 0)
882 #define CLK_DIV_CPERI1_VAL 0x3f3f0000
887 /* Errors that we can encourter in low-level setup */
890 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
891 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
895 * Memory variant specific initialization code for DDR3
897 * @param mem Memory timings for this memory type.
898 * @param reset Reset DDR PHY during initialization.
899 * @return 0 if ok, SETUP_ERR_... if there is a problem
901 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
903 /* Memory variant specific initialization code for LPDDR3 */
904 void lpddr3_mem_ctrl_init(void);
907 * Configure ZQ I/O interface
909 * @param mem Memory timings for this memory type.
910 * @param phy0_con16 Register address for dmc_phy0->phy_con16
911 * @param phy1_con16 Register address for dmc_phy1->phy_con16
912 * @param phy0_con17 Register address for dmc_phy0->phy_con17
913 * @param phy1_con17 Register address for dmc_phy1->phy_con17
914 * @return 0 if ok, -1 on error
916 int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
917 uint32_t *phy1_con16, uint32_t *phy0_con17,
918 uint32_t *phy1_con17);
920 * Send NOP and MRS/EMRS Direct commands
922 * @param mem Memory timings for this memory type.
923 * @param directcmd Register address for dmc_phy->directcmd
925 void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
928 * Send PALL Direct commands
930 * @param mem Memory timings for this memory type.
931 * @param directcmd Register address for dmc_phy->directcmd
933 void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
936 * Reset the DLL. This function is common between DDR3 and LPDDR2.
937 * However, the reset value is different. So we are passing a flag
938 * ddr_mode to distinguish between LPDDR2 and DDR3.
940 * @param phycontrol0 Register address for dmc_phy->phycontrol0
941 * @param ddr_mode Type of DDR memory
943 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);