2 * Machine Specific Values for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _SMDK5250_SETUP_H
10 #define _SMDK5250_SETUP_H
13 #include <asm/arch/dmc.h>
15 #define NOT_AVAILABLE 0
16 #define DATA_MASK 0xFFFFF
18 #define ENABLE_BIT 0x1
19 #define DISABLE_BIT 0x0
20 #define CA_SWAP_EN (1 << 0)
23 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
25 /* MEMCONTROL register bit fields */
26 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
27 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
28 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
29 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
30 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
31 #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
32 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
34 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
35 #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
36 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
38 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
40 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
41 #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
43 #define DMC_MEMCONTROL_BL_8 (3 << 20)
44 #define DMC_MEMCONTROL_BL_4 (2 << 20)
46 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
48 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
49 #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
50 #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
51 #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
53 /* MEMCONFIG0 register bit fields */
54 #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
55 #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
56 #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
57 #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
58 #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
59 #define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
61 #define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
62 #define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
63 #define DMC_MEMBASECONFIG_VAL(x) ( \
64 DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
65 DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
69 * As we use channel interleaving, therefore value of the base address
70 * register must be set as half of the bus base address
71 * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
72 * we need to set half 0x10 to the membaseconfigx registers
73 * see exynos5420 UM section 17.17.3.21 for more.
75 #define DMC_CHIP_BASE_0 0x10
76 #define DMC_CHIP_BASE_1 0x50
77 #define DMC_CHIP_MASK 0x7C0
79 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
80 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
82 #define DMC_PRECHCONFIG_VAL 0xFF000000
83 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
85 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
86 #define DFI_INIT_START (1 << 28)
87 #define EMPTY (1 << 8)
88 #define AREF_EN (1 << 5)
90 #define DFI_INIT_COMPLETE_CHO (1 << 2)
91 #define DFI_INIT_COMPLETE_CH1 (1 << 3)
93 #define RDLVL_COMPLETE_CHO (1 << 14)
94 #define RDLVL_COMPLETE_CH1 (1 << 15)
96 #define CLK_STOP_EN (1 << 0)
97 #define DPWRDN_EN (1 << 1)
98 #define DSREF_EN (1 << 5)
100 /* COJCONTROL register bit fields */
101 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
102 #define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
103 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
104 #define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
105 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
106 #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
107 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
108 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
109 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
111 #define DMC_CONCONTROL_VAL 0x1FFF2101
113 #define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
114 | DMC_CONCONTROL_AREF_EN_ENABLE \
115 | DMC_CONCONTROL_IO_PD_CON_ENABLE
117 #define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
120 #define HPM_RATIO 0x2
121 #define COPY_RATIO 0x0
123 /* CLK_DIV_CPU1 = 0x00000003 */
124 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
128 #define CLK_SRC_CORE0_VAL 0x00000000
131 #define CLK_SRC_CORE1_VAL 0x100
134 #define CLK_DIV_CORE0_VAL 0x00120000
137 #define CLK_DIV_CORE1_VAL 0x07070700
140 #define CLK_DIV_SYSRGT_VAL 0x00000111
143 #define CLK_DIV_ACP_VAL 0x12
146 #define CLK_DIV_SYSLFT_VAL 0x00000311
148 #define MUX_APLL_SEL_MASK (1 << 0)
149 #define MUX_MPLL_SEL_MASK (1 << 8)
150 #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
151 #define MUX_CPLL_SEL_MASK (1 << 8)
152 #define MUX_EPLL_SEL_MASK (1 << 12)
153 #define MUX_VPLL_SEL_MASK (1 << 16)
154 #define MUX_GPLL_SEL_MASK (1 << 28)
155 #define MUX_BPLL_SEL_MASK (1 << 0)
156 #define MUX_HPM_SEL_MASK (1 << 20)
157 #define HPM_SEL_SCLK_MPLL (1 << 21)
158 #define PLL_LOCKED (1 << 29)
159 #define APLL_CON0_LOCKED (1 << 29)
160 #define MPLL_CON0_LOCKED (1 << 29)
161 #define BPLL_CON0_LOCKED (1 << 29)
162 #define CPLL_CON0_LOCKED (1 << 29)
163 #define EPLL_CON0_LOCKED (1 << 29)
164 #define GPLL_CON0_LOCKED (1 << 29)
165 #define VPLL_CON0_LOCKED (1 << 29)
166 #define CLK_REG_DISABLE 0x0
167 #define TOP2_VAL 0x0110000
169 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
170 #define SPI0_ISP_SEL 6
171 #define SPI1_ISP_SEL 6
172 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
173 | (SPI0_ISP_SEL << 0)
175 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
176 #define SPI0_ISP_RATIO 0xf
177 #define SPI1_ISP_RATIO 0xf
178 #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
179 | (SPI0_ISP_RATIO << 0)
182 #define MMC2_RATIO_MASK 0xf
183 #define MMC2_RATIO_VAL 0x3
184 #define MMC2_RATIO_OFFSET 0
186 #define MMC2_PRE_RATIO_MASK 0xff
187 #define MMC2_PRE_RATIO_VAL 0x9
188 #define MMC2_PRE_RATIO_OFFSET 8
190 #define MMC3_RATIO_MASK 0xf
191 #define MMC3_RATIO_VAL 0x1
192 #define MMC3_RATIO_OFFSET 16
194 #define MMC3_PRE_RATIO_MASK 0xff
195 #define MMC3_PRE_RATIO_VAL 0x0
196 #define MMC3_PRE_RATIO_OFFSET 24
199 #define CLK_SRC_LEX_VAL 0x0
202 #define CLK_DIV_LEX_VAL 0x10
205 #define CLK_DIV_R0X_VAL 0x10
208 #define CLK_DIV_R1X_VAL 0x10
211 #define CLK_DIV_ISP2_VAL 0x1
214 #define SRC_KFC_HPM_SEL (1 << 15)
217 #define CLK_SRC_KFC_VAL 0x00008001
220 #define CLK_DIV_KFC_VAL 0x03300110
223 #define CLK_DIV2_RATIO 0x10111150
226 #define CLK_DIV4_RATIO 0x00000003
229 #define CLK_DIV_G2D 0x00000010
233 * For DP, divisor should be 2
235 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
237 /* CLK_GATE_IP_DISP1 */
238 #define CLK_GATE_DP1_ALLOW (1 << 4)
241 #define AUDIO0_SEL_EPLL (0x6 << 28)
242 #define AUDIO0_RATIO 0x5
243 #define PCM0_RATIO 0x3
244 #define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
247 #define MUX_MCLK_CDR_MSPLL (1 << 4)
248 #define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
249 #define BPLL_SEL_MASK 0x7
252 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
253 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
255 #define PHY_CON0_RESET_VAL 0x17020a40
256 #define P0_CMD_EN (1 << 14)
257 #define BYTE_RDLVL_EN (1 << 13)
258 #define CTRL_SHGATE (1 << 8)
260 #define PHY_CON1_RESET_VAL 0x09210100
261 #define RDLVL_PASS_ADJ_VAL 0x6
262 #define RDLVL_PASS_ADJ_OFFSET 16
263 #define CTRL_GATEDURADJ_MASK (0xf << 20)
264 #define READ_LEVELLING_DDR3 0x0100
266 #define PHY_CON2_RESET_VAL 0x00010004
267 #define INIT_DESKEW_EN (1 << 6)
268 #define DLL_DESKEW_EN (1 << 12)
269 #define RDLVL_GATE_EN (1 << 24)
270 #define RDLVL_EN (1 << 25)
271 #define RDLVL_INCR_ADJ (0x1 << 16)
274 #define DREX_PAUSE_EN (1 << 0)
276 #define BYPASS_EN (1 << 22)
279 #define PHY_CON0_VAL 0x17021A00
281 #define PHY_CON12_RESET_VAL 0x10100070
282 #define PHY_CON12_VAL 0x10107F50
283 #define CTRL_START (1 << 6)
284 #define CTRL_DLL_ON (1 << 5)
285 #define CTRL_FORCE_MASK (0x7F << 8)
286 #define CTRL_LOCK_COARSE_MASK (0x7F << 10)
287 #define CTRL_FINE_LOCKED 0x7
289 #define CTRL_OFFSETD_RESET_VAL 0x8
290 #define CTRL_OFFSETD_VAL 0x7F
292 #define CTRL_OFFSETR0 0x7F
293 #define CTRL_OFFSETR1 0x7F
294 #define CTRL_OFFSETR2 0x7F
295 #define CTRL_OFFSETR3 0x7F
296 #define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
297 CTRL_OFFSETR1 << 8 | \
298 CTRL_OFFSETR2 << 16 | \
300 #define PHY_CON4_RESET_VAL 0x08080808
302 #define CTRL_OFFSETW0 0x7F
303 #define CTRL_OFFSETW1 0x7F
304 #define CTRL_OFFSETW2 0x7F
305 #define CTRL_OFFSETW3 0x7F
306 #define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
307 CTRL_OFFSETW1 << 8 | \
308 CTRL_OFFSETW2 << 16 | \
310 #define PHY_CON6_RESET_VAL 0x08080808
312 #define PHY_CON14_RESET_VAL 0x001F0000
313 #define CTRL_PULLD_DQS 0xF
314 #define CTRL_PULLD_DQS_OFFSET 0
316 /* ZQ Configurations */
317 #define PHY_CON16_RESET_VAL 0x08000304
319 #define ZQ_CLK_EN (1 << 27)
320 #define ZQ_CLK_DIV_EN (1 << 18)
321 #define ZQ_MANUAL_STR (1 << 1)
322 #define ZQ_DONE (1 << 0)
323 #define ZQ_MODE_DDS_OFFSET 24
325 #define CTRL_RDLVL_GATE_ENABLE 1
326 #define CTRL_RDLVL_GATE_DISABLE 0
327 #define CTRL_RDLVL_DATA_ENABLE 2
330 #define DIRECT_CMD_NOP 0x07000000
331 #define DIRECT_CMD_PALL 0x01000000
332 #define DIRECT_CMD_ZQINIT 0x0a000000
333 #define DIRECT_CMD_CHANNEL_SHIFT 28
334 #define DIRECT_CMD_CHIP_SHIFT 20
335 #define DIRECT_CMD_BANK_SHIFT 16
336 #define DIRECT_CMD_REFA (5 << 24)
337 #define DIRECT_CMD_MRS1 0x71C00
338 #define DIRECT_CMD_MRS2 0x10BFC
339 #define DIRECT_CMD_MRS3 0x0050C
340 #define DIRECT_CMD_MRS4 0x00868
341 #define DIRECT_CMD_MRS5 0x00C04
344 #define IMPEDANCE_48_OHM 4
345 #define IMPEDANCE_40_OHM 5
346 #define IMPEDANCE_34_OHM 6
347 #define IMPEDANCE_30_OHM 7
348 #define PHY_CON39_VAL_48_OHM 0x09240924
349 #define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
350 #define PHY_CON39_VAL_34_OHM 0x0DB60DB6
351 #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
353 #define CTRL_BSTLEN_OFFSET 8
354 #define CTRL_RDLAT_OFFSET 0
356 #define CMD_DEFAULT_LPDDR3 0xF
357 #define CMD_DEFUALT_OFFSET 0
358 #define T_WRDATA_EN 0x7
359 #define T_WRDATA_EN_DDR3 0x8
360 #define T_WRDATA_EN_OFFSET 16
361 #define T_WRDATA_EN_MASK 0x1f
363 #define PHY_CON31_VAL 0x0C183060
364 #define PHY_CON32_VAL 0x60C18306
365 #define PHY_CON33_VAL 0x00000030
367 #define PHY_CON31_RESET_VAL 0x0
368 #define PHY_CON32_RESET_VAL 0x0
369 #define PHY_CON33_RESET_VAL 0x0
371 #define SL_DLL_DYN_CON_EN (1 << 1)
372 #define FP_RESYNC (1 << 3)
373 #define CTRL_START (1 << 6)
375 #define DMC_AREF_EN (1 << 5)
376 #define DMC_CONCONTROL_EMPTY (1 << 8)
377 #define DFI_INIT_START (1 << 28)
379 #define DMC_MEMCONTROL_VAL 0x00312700
380 #define CLK_STOP_EN (1 << 0)
381 #define DPWRDN_EN (1 << 1)
382 #define DSREF_EN (1 << 5)
384 #define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
385 #define MEMBASECONFIG_CHIP_MASK_OFFSET 0
386 #define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
387 #define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
388 #define CHIP_BASE_OFFSET 16
390 #define MEMCONFIG_VAL 0x1323
391 #define PRECHCONFIG_DEFAULT_VAL 0xFF000000
392 #define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
394 #define TIMINGAREF_VAL 0x5d
395 #define TIMINGROW_VAL 0x345A8692
396 #define TIMINGDATA_VAL 0x3630065C
397 #define TIMINGPOWER_VAL 0x50380336
398 #define DFI_INIT_COMPLETE (1 << 3)
400 #define BRBRSVCONTROL_VAL 0x00000033
401 #define BRBRSVCONFIG_VAL 0x88778877
403 /* Clock Gating Control (CGCONTROL) register */
404 #define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
405 #define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
406 #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
407 #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
408 #define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
409 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
411 /* DMC PHY Control0 register */
412 #define PHY_CONTROL0_RESET_VAL 0x0
413 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
414 #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
415 #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
416 #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
418 /* Driver strength for CK, CKE, CS & CA */
419 #define IMP_OUTPUT_DRV_40_OHM 0x5
420 #define IMP_OUTPUT_DRV_30_OHM 0x7
421 #define DA_3_DS_OFFSET 25
422 #define DA_2_DS_OFFSET 22
423 #define DA_1_DS_OFFSET 19
424 #define DA_0_DS_OFFSET 16
425 #define CA_CK_DRVR_DS_OFFSET 9
426 #define CA_CKE_DRVR_DS_OFFSET 6
427 #define CA_CS_DRVR_DS_OFFSET 3
428 #define CA_ADR_DRVR_DS_OFFSET 0
430 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
431 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
434 * Definitions that differ with SoC's.
435 * Below is the part defining macros for smdk5250.
436 * Else part introduces macros for smdk5420.
438 #ifndef CONFIG_SMDK5420
441 #define APLL_CON1_VAL (0x00203800)
444 #define MPLL_CON1_VAL (0x00203800)
447 #define CPLL_CON1_VAL (0x00203800)
450 #define DPLL_CON1_VAL (NOT_AVAILABLE)
453 #define GPLL_CON1_VAL (0x00203800)
455 /* EPLL_CON1, CON2 */
456 #define EPLL_CON1_VAL 0x00000000
457 #define EPLL_CON2_VAL 0x00000080
459 /* VPLL_CON1, CON2 */
460 #define VPLL_CON1_VAL 0x00000000
461 #define VPLL_CON2_VAL 0x00000080
463 /* RPLL_CON1, CON2 */
464 #define RPLL_CON1_VAL NOT_AVAILABLE
465 #define RPLL_CON2_VAL NOT_AVAILABLE
468 #define BPLL_CON1_VAL 0x00203800
471 #define SPLL_CON1_VAL NOT_AVAILABLE
474 #define IPLL_CON1_VAL NOT_AVAILABLE
477 #define KPLL_CON1_VAL NOT_AVAILABLE
480 #define CLK_SRC_ISP_VAL NOT_AVAILABLE
481 #define CLK_DIV_ISP0_VAL 0x31
482 #define CLK_DIV_ISP1_VAL 0x0
485 #define CLK_SRC_FSYS0_VAL 0x66666
486 #define CLK_DIV_FSYS0_VAL 0x0BB00000
487 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
488 #define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
491 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
492 #define MUX_HPM_SEL 0
493 #define MUX_CPU_SEL 0
494 #define MUX_APLL_SEL 1
496 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
497 | (MUX_CPU_SEL << 16) \
501 #define CLK_SRC_CDREX_VAL 0x1
504 #define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
505 #define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
507 /* CLK_DIV_CPU0_VAL */
508 #define CLK_DIV_CPU0_VAL NOT_AVAILABLE
510 #define MCLK_CDREX2_RATIO 0x0
511 #define ACLK_EFCON_RATIO 0x1
512 #define MCLK_DPHY_RATIO 0x1
513 #define MCLK_CDREX_RATIO 0x1
514 #define ACLK_C2C_200_RATIO 0x1
515 #define C2C_CLK_400_RATIO 0x1
516 #define PCLK_CDREX_RATIO 0x1
517 #define ACLK_CDREX_RATIO 0x1
519 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
520 | (C2C_CLK_400_RATIO << 6) \
521 | (PCLK_CDREX_RATIO << 4) \
522 | (ACLK_CDREX_RATIO))
525 #define MUX_ACLK_300_GSCL_SEL 0x0
526 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
527 #define MUX_ACLK_400_G3D_MID_SEL 0x0
528 #define MUX_ACLK_333_SEL 0x0
529 #define MUX_ACLK_300_DISP1_SEL 0x0
530 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
531 #define MUX_ACLK_200_SEL 0x0
532 #define MUX_ACLK_166_SEL 0x0
533 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
534 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
535 | (MUX_ACLK_400_G3D_MID_SEL << 20) \
536 | (MUX_ACLK_333_SEL << 16) \
537 | (MUX_ACLK_300_DISP1_SEL << 15) \
538 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
539 | (MUX_ACLK_200_SEL << 12) \
540 | (MUX_ACLK_166_SEL << 8))
543 #define MUX_ACLK_400_G3D_SEL 0x1
544 #define MUX_ACLK_400_ISP_SEL 0x0
545 #define MUX_ACLK_400_IOP_SEL 0x0
546 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
547 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
548 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
549 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
550 |(MUX_ACLK_400_ISP_SEL << 24) \
551 |(MUX_ACLK_400_IOP_SEL << 20) \
552 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
553 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
554 |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
557 #define MUX_GPLL_SEL 0x1
558 #define MUX_BPLL_USER_SEL 0x0
559 #define MUX_MPLL_USER_SEL 0x0
560 #define MUX_VPLL_SEL 0x1
561 #define MUX_EPLL_SEL 0x1
562 #define MUX_CPLL_SEL 0x1
563 #define VPLLSRC_SEL 0x0
564 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
565 | (MUX_BPLL_USER_SEL << 24) \
566 | (MUX_MPLL_USER_SEL << 20) \
567 | (MUX_VPLL_SEL << 16) \
568 | (MUX_EPLL_SEL << 12) \
569 | (MUX_CPLL_SEL << 8) \
572 #define MUX_ACLK_333_SUB_SEL 0x1
573 #define MUX_ACLK_400_SUB_SEL 0x1
574 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
575 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
576 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
577 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
578 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
579 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
580 #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
581 | (MUX_ACLK_400_SUB_SEL << 20) \
582 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
583 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
584 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
585 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
586 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
587 | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
589 #define CLK_SRC_TOP4_VAL NOT_AVAILABLE
590 #define CLK_SRC_TOP5_VAL NOT_AVAILABLE
591 #define CLK_SRC_TOP6_VAL NOT_AVAILABLE
592 #define CLK_SRC_TOP7_VAL NOT_AVAILABLE
595 #define ACLK_300_DISP1_RATIO 0x2
596 #define ACLK_400_G3D_RATIO 0x0
597 #define ACLK_333_RATIO 0x0
598 #define ACLK_266_RATIO 0x2
599 #define ACLK_200_RATIO 0x3
600 #define ACLK_166_RATIO 0x1
601 #define ACLK_133_RATIO 0x1
602 #define ACLK_66_RATIO 0x5
604 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
605 | (ACLK_400_G3D_RATIO << 24) \
606 | (ACLK_333_RATIO << 20) \
607 | (ACLK_266_RATIO << 16) \
608 | (ACLK_200_RATIO << 12) \
609 | (ACLK_166_RATIO << 8) \
610 | (ACLK_133_RATIO << 4) \
614 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
615 #define ACLK_66_PRE_RATIO 0x1
616 #define ACLK_400_ISP_RATIO 0x1
617 #define ACLK_400_IOP_RATIO 0x1
618 #define ACLK_300_GSCL_RATIO 0x2
620 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
621 | (ACLK_66_PRE_RATIO << 24) \
622 | (ACLK_400_ISP_RATIO << 20) \
623 | (ACLK_400_IOP_RATIO << 16) \
624 | (ACLK_300_GSCL_RATIO << 12))
626 #define CLK_DIV_TOP2_VAL NOT_AVAILABLE
628 /* PLL Lock Value Factor */
629 #define PLL_LOCK_FACTOR 250
630 #define PLL_X_LOCK_FACTOR 3000
638 /* SRC_CLOCK = SCLK_MPLL */
639 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
640 | (UART3_SEL << 12) \
646 /* SRC_CLOCK = SCLK_MPLL */
650 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
655 #define UART5_RATIO 7
656 #define UART4_RATIO 7
657 #define UART3_RATIO 7
658 #define UART2_RATIO 7
659 #define UART1_RATIO 7
660 #define UART0_RATIO 7
662 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
663 | (UART2_RATIO << 8) \
664 | (UART1_RATIO << 4) \
667 #define SPI1_RATIO 0x7
668 #define SPI0_RATIO 0xf
669 #define SPI1_SUB_RATIO 0x0
670 #define SPI0_SUB_RATIO 0x0
671 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
672 | ((SPI1_RATIO << 16) \
673 | (SPI0_SUB_RATIO << 8) \
674 | (SPI0_RATIO << 0)))
677 #define SPI2_RATIO 0xf
678 #define SPI2_SUB_RATIO 0x0
679 #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
684 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
688 #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
690 /* CLK_SRC_DISP1_0 */
691 #define CLK_SRC_DISP1_0_VAL 0x6
692 #define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
694 #define APLL_FOUT (1 << 0)
695 #define KPLL_FOUT NOT_AVAILABLE
697 #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
700 #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
703 #define APLL_CON1_VAL (0x0020F300)
706 #define MPLL_CON1_VAL (0x0020F300)
710 #define CPLL_CON1_VAL 0x0020f300
713 #define DPLL_CON1_VAL (0x0020F300)
716 #define GPLL_CON1_VAL (NOT_AVAILABLE)
719 /* EPLL_CON1, CON2 */
720 #define EPLL_CON1_VAL 0x00000000
721 #define EPLL_CON2_VAL 0x00000080
723 /* VPLL_CON1, CON2 */
724 #define VPLL_CON1_VAL 0x0020f300
725 #define VPLL_CON2_VAL NOT_AVAILABLE
727 /* RPLL_CON1, CON2 */
728 #define RPLL_CON1_VAL 0x00000000
729 #define RPLL_CON2_VAL 0x00000080
732 #define BPLL_CON1_VAL 0x0020f300
735 #define SPLL_CON1_VAL 0x0020f300
738 #define IPLL_CON1_VAL 0x00000080
741 #define KPLL_CON1_VAL 0x200000
744 #define CLK_SRC_ISP_VAL 0x33366000
745 #define CLK_DIV_ISP0_VAL 0x13131300
746 #define CLK_DIV_ISP1_VAL 0xbb110202
750 #define CLK_SRC_FSYS0_VAL 0x33033300
751 #define CLK_DIV_FSYS0_VAL 0x0
752 #define CLK_DIV_FSYS1_VAL 0x04f13c4f
753 #define CLK_DIV_FSYS2_VAL 0x041d0000
756 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
757 #define MUX_HPM_SEL 1
758 #define MUX_CPU_SEL 0
759 #define MUX_APLL_SEL 1
761 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
762 | (MUX_CPU_SEL << 16) \
766 #define CLK_SRC_CDREX_VAL 0x00000011
769 #define CLK_DIV_CDREX0_VAL 0x30010100
770 #define CLK_DIV_CDREX1_VAL 0x300
772 #define CLK_DIV_CDREX_VAL 0x17010100
774 /* CLK_DIV_CPU0_VAL */
775 #define CLK_DIV_CPU0_VAL 0x01440020
778 #define CLK_SRC_TOP0_VAL 0x12221222
779 #define CLK_SRC_TOP1_VAL 0x00100200
780 #define CLK_SRC_TOP2_VAL 0x11101000
781 #define CLK_SRC_TOP3_VAL 0x11111111
782 #define CLK_SRC_TOP4_VAL 0x11110111
783 #define CLK_SRC_TOP5_VAL 0x11111100
784 #define CLK_SRC_TOP6_VAL 0x11110111
785 #define CLK_SRC_TOP7_VAL 0x00022200
788 #define CLK_DIV_TOP0_VAL 0x23712311
789 #define CLK_DIV_TOP1_VAL 0x13100B00
790 #define CLK_DIV_TOP2_VAL 0x11101100
792 /* PLL Lock Value Factor */
793 #define PLL_LOCK_FACTOR 200
794 #define PLL_X_LOCK_FACTOR 3000
804 /* SRC_CLOCK = SCLK_RPLL */
805 #define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
807 | (UART4_SEL << 20) \
808 | (UART3_SEL << 16) \
809 | (UART2_SEL << 12) \
814 /* SRC_CLOCK = SCLK_EPLL */
821 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
824 | (AUDIO2_SEL << 16) \
825 | (AUDIO2_SEL << 12) \
830 #define UART4_RATIO 9
831 #define UART3_RATIO 9
832 #define UART2_RATIO 9
833 #define UART1_RATIO 9
834 #define UART0_RATIO 9
836 #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
837 | (UART4_RATIO << 24) \
838 | (UART3_RATIO << 20) \
839 | (UART2_RATIO << 16) \
840 | (UART1_RATIO << 12) \
841 | (UART0_RATIO << 8))
843 #define SPI2_RATIO 0x1
844 #define SPI1_RATIO 0x1
845 #define SPI0_RATIO 0x1
846 #define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
847 | (SPI1_RATIO << 24) \
848 | (SPI0_RATIO << 20))
851 #define PCM2_RATIO 0x3
852 #define PCM1_RATIO 0x3
853 #define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
854 | (PCM1_RATIO << 16))
857 #define AUDIO2_RATIO 0x5
858 #define AUDIO1_RATIO 0x5
859 #define AUDIO0_RATIO 0x5
860 #define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
861 | (AUDIO1_RATIO << 24) \
862 | (AUDIO0_RATIO << 20))
865 #define SPI2_PRE_RATIO 0x2
866 #define SPI1_PRE_RATIO 0x2
867 #define SPI0_PRE_RATIO 0x2
868 #define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
869 | (SPI1_PRE_RATIO << 16) \
870 | (SPI0_PRE_RATIO << 8))
872 /* CLK_SRC_DISP1_0 */
873 #define CLK_SRC_DISP1_0_VAL 0x10666600
874 #define CLK_DIV_DISP1_0_VAL 0x01050211
876 #define APLL_FOUT (1 << 0)
877 #define KPLL_FOUT (1 << 0)
879 #define CLK_DIV_CPERI1_VAL 0x3f3f0000
884 /* Errors that we can encourter in low-level setup */
887 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
888 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
892 * Memory variant specific initialization code for DDR3
894 * @param mem Memory timings for this memory type.
895 * @param reset Reset DDR PHY during initialization.
896 * @return 0 if ok, SETUP_ERR_... if there is a problem
898 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
900 /* Memory variant specific initialization code for LPDDR3 */
901 void lpddr3_mem_ctrl_init(void);
904 * Configure ZQ I/O interface
906 * @param mem Memory timings for this memory type.
907 * @param phy0_con16 Register address for dmc_phy0->phy_con16
908 * @param phy1_con16 Register address for dmc_phy1->phy_con16
909 * @param phy0_con17 Register address for dmc_phy0->phy_con17
910 * @param phy1_con17 Register address for dmc_phy1->phy_con17
911 * @return 0 if ok, -1 on error
913 int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
914 uint32_t *phy1_con16, uint32_t *phy0_con17,
915 uint32_t *phy1_con17);
917 * Send NOP and MRS/EMRS Direct commands
919 * @param mem Memory timings for this memory type.
920 * @param directcmd Register address for dmc_phy->directcmd
922 void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
925 * Send PALL Direct commands
927 * @param mem Memory timings for this memory type.
928 * @param directcmd Register address for dmc_phy->directcmd
930 void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
933 * Reset the DLL. This function is common between DDR3 and LPDDR2.
934 * However, the reset value is different. So we are passing a flag
935 * ddr_mode to distinguish between LPDDR2 and DDR3.
937 * @param phycontrol0 Register address for dmc_phy->phycontrol0
938 * @param ddr_mode Type of DDR memory
940 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);