2 * Lowlevel setup for EXYNOS5 based board
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/dmc.h>
30 #include <asm/arch/power.h>
31 #include <asm/arch/tzpc.h>
32 #include <asm/arch/periph.h>
33 #include <asm/arch/pinmux.h>
34 #include <asm/arch/system.h>
35 #include <asm/armv7.h>
36 #include "common_setup.h"
37 #include "exynos5_setup.h"
39 /* These are the things we can do during low-level init */
43 DO_MEM_RESET = 1 << 2,
48 #ifdef CONFIG_EXYNOS5420
50 * Power up secondary CPUs.
52 static void secondary_cpu_start(void)
54 v7_enable_smp(EXYNOS5420_INFORM_BASE);
56 branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
60 * This is the entry point of hotplug-in and
63 static void low_power_start(void)
65 uint32_t val, reg_val;
67 reg_val = readl(EXYNOS5420_SPARE_BASE);
68 if (reg_val != CPU_RST_FLAG_VAL) {
69 writel(0x0, CONFIG_LOWPOWER_FLAG);
73 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
74 if (reg_val != (uint32_t)&low_power_start) {
75 /* Store jump address as low_power_start if not present */
76 writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
81 /* Set the CPU to SVC32 mode */
84 #ifndef CONFIG_SYS_L2CACHE_OFF
85 /* Read MIDR for Primary Part Number */
93 v7_enable_l2_hazard_detect();
97 /* Invalidate L1 & TLB */
102 /* Disable MMU stuff and caches */
105 val &= ~((0x2 << 12) | 0x7);
106 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
109 /* CPU state is hotplug or reset */
110 secondary_cpu_start();
112 /* Core should not enter into WFI here */
117 * Pointer to this function is stored in iRam which is used
118 * for jump and power down of a specific core.
120 static void power_down_core(void)
122 uint32_t tmp, core_id, core_config;
124 /* Get the unique core id */
126 * Multiprocessor Affinity Register
132 core_id = (core_id >> 6) & ~3;
136 /* Set the status of the core to low */
137 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
138 core_config += EXYNOS5420_CPU_CONFIG_BASE;
139 writel(0x0, core_config);
146 * Configurations for secondary cores are inapt at this stage.
147 * Reconfigure secondary cores. Shutdown and change the status
148 * of all cores except the primary core.
150 static void secondary_cores_configure(void)
152 /* Clear secondary boot iRAM base */
153 writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
155 /* set lowpower flag and address */
156 writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
157 writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
158 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
159 /* Store jump address for power down */
160 writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
162 /* Need all core power down check */
167 extern void relocate_wait_code(void);
170 int do_lowlevel_init(void)
172 uint32_t reset_status;
177 #ifndef CONFIG_SYS_L2CACHE_OFF
179 * Init L2 cache parameters here for use by boot and resume
181 * These are here instead of in v7_outer_cache_enable() so that the
182 * L2 cache settings get properly set even at resume time or if we're
183 * running U-Boot with the cache off. The kernel still needs us to
187 configure_l2_actlr();
192 #ifdef CONFIG_EXYNOS5420
193 relocate_wait_code();
195 /* Reconfigure secondary cores */
196 secondary_cores_configure();
199 reset_status = get_reset_status();
201 switch (reset_status) {
202 case S5P_CHECK_SLEEP:
203 actions = DO_CLOCKS | DO_WAKEUP;
205 case S5P_CHECK_DIDLE:
210 /* This is a normal boot (not a wake from sleep) */
211 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
214 if (actions & DO_POWER)
217 if (actions & DO_CLOCKS) {
219 mem_ctrl_init(actions & DO_MEM_RESET);
223 return actions & DO_WAKEUP;