2 * Lowlevel setup for EXYNOS5 based board
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/dmc.h>
30 #include <asm/arch/power.h>
31 #include <asm/arch/tzpc.h>
32 #include <asm/arch/periph.h>
33 #include <asm/arch/pinmux.h>
34 #include <asm/arch/system.h>
35 #include <asm/armv7.h>
36 #include "common_setup.h"
37 #include "exynos5_setup.h"
39 /* These are the things we can do during low-level init */
43 DO_MEM_RESET = 1 << 2,
48 #ifdef CONFIG_EXYNOS5420
50 * Enable ECC by setting L2CTLR[21].
51 * Set L2CTLR[7] to make tag ram latency 3 cycles and
52 * set L2CTLR[1] to make data ram latency 3 cycles.
53 * We need to make RAM latency of 3 cycles here because cores
54 * power ON and OFF while switching. And everytime a core powers
55 * ON, iROM provides it a default L2CTLR value 0x400 which stands
56 * for TAG RAM setup of 1 cycle. Hence, we face a need of
57 * restoring data and tag latency values.
59 static void configure_l2_ctlr(void)
71 * Set L2ACTLR[27] to prevent the clock generator from stopping
73 * Set L2ACTLR[3] to disable clean/evict push to external.
75 static void configure_l2_actlr(void)
86 * Power up secondary CPUs.
88 static void secondary_cpu_start(void)
90 v7_enable_smp(EXYNOS5420_INFORM_BASE);
92 branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
96 * This is the entry point of hotplug-in and
99 static void low_power_start(void)
101 uint32_t val, reg_val;
103 reg_val = readl(EXYNOS5420_SPARE_BASE);
104 if (reg_val != CPU_RST_FLAG_VAL) {
105 writel(0x0, CONFIG_LOWPOWER_FLAG);
109 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
110 if (reg_val != (uint32_t)&low_power_start) {
111 /* Store jump address as low_power_start if not present */
112 writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
117 /* Set the CPU to SVC32 mode */
120 #ifndef CONFIG_SYS_L2CACHE_OFF
121 /* Read MIDR for Primary Part Number */
128 configure_l2_actlr();
129 v7_enable_l2_hazard_detect();
133 /* Invalidate L1 & TLB */
138 /* Disable MMU stuff and caches */
141 val &= ~((0x2 << 12) | 0x7);
142 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
145 /* CPU state is hotplug or reset */
146 secondary_cpu_start();
148 /* Core should not enter into WFI here */
153 * Pointer to this function is stored in iRam which is used
154 * for jump and power down of a specific core.
156 static void power_down_core(void)
158 uint32_t tmp, core_id, core_config;
160 /* Get the unique core id */
162 * Multiprocessor Affinity Register
168 core_id = (core_id >> 6) & ~3;
172 /* Set the status of the core to low */
173 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
174 core_config += EXYNOS5420_CPU_CONFIG_BASE;
175 writel(0x0, core_config);
182 * Configurations for secondary cores are inapt at this stage.
183 * Reconfigure secondary cores. Shutdown and change the status
184 * of all cores except the primary core.
186 static void secondary_cores_configure(void)
190 v7_enable_l2_hazard_detect();
192 /* Clear secondary boot iRAM base */
193 writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
195 /* set lowpower flag and address */
196 writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
197 writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
198 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
199 /* Store jump address for power down */
200 writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
202 /* Need all core power down check */
207 extern void relocate_wait_code(void);
210 int do_lowlevel_init(void)
212 uint32_t reset_status;
217 #ifdef CONFIG_EXYNOS5420
218 relocate_wait_code();
220 /* Reconfigure secondary cores */
221 secondary_cores_configure();
224 reset_status = get_reset_status();
226 switch (reset_status) {
227 case S5P_CHECK_SLEEP:
228 actions = DO_CLOCKS | DO_WAKEUP;
230 case S5P_CHECK_DIDLE:
235 /* This is a normal boot (not a wake from sleep) */
236 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
239 if (actions & DO_POWER)
242 if (actions & DO_CLOCKS) {
244 mem_ctrl_init(actions & DO_MEM_RESET);
248 return actions & DO_WAKEUP;