2 * Copyright (c) 2012 Samsung Electronics.
3 * Abhilash Kesavan <a.kesavan@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/gpio.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/sromc.h>
14 static void exynos5_uart_config(int peripheral)
16 struct exynos5_gpio_part1 *gpio1 =
17 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
18 struct s5p_gpio_bank *bank;
43 debug("%s: invalid peripheral %d", __func__, peripheral);
46 for (i = start; i < start + count; i++) {
47 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
48 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
52 static void exynos5420_uart_config(int peripheral)
54 struct exynos5420_gpio_part1 *gpio1 =
55 (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
56 struct s5p_gpio_bank *bank;
81 debug("%s: invalid peripheral %d", __func__, peripheral);
85 for (i = start; i < start + count; i++) {
86 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
87 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
91 static int exynos5_mmc_config(int peripheral, int flags)
93 struct exynos5_gpio_part1 *gpio1 =
94 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
95 struct s5p_gpio_bank *bank, *bank_ext;
96 int i, start = 0, gpio_func = 0;
99 case PERIPH_ID_SDMMC0:
101 bank_ext = &gpio1->c1;
103 gpio_func = GPIO_FUNC(0x2);
105 case PERIPH_ID_SDMMC1:
109 case PERIPH_ID_SDMMC2:
111 bank_ext = &gpio1->c4;
113 gpio_func = GPIO_FUNC(0x3);
115 case PERIPH_ID_SDMMC3:
120 debug("%s: invalid peripheral %d", __func__, peripheral);
123 if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
124 debug("SDMMC device %d does not support 8bit mode",
128 if (flags & PINMUX_FLAG_8BIT_MODE) {
129 for (i = start; i <= (start + 3); i++) {
130 s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
131 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
132 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
135 for (i = 0; i < 2; i++) {
136 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
137 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
138 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
140 for (i = 3; i <= 6; i++) {
141 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
142 s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
143 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
149 static int exynos5420_mmc_config(int peripheral, int flags)
151 struct exynos5420_gpio_part3 *gpio3 =
152 (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
153 struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
156 switch (peripheral) {
157 case PERIPH_ID_SDMMC0:
159 bank_ext = &gpio3->c3;
162 case PERIPH_ID_SDMMC1:
164 bank_ext = &gpio3->d1;
167 case PERIPH_ID_SDMMC2:
174 debug("%s: invalid peripheral %d", __func__, peripheral);
178 if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
179 debug("SDMMC device %d does not support 8bit mode",
184 if (flags & PINMUX_FLAG_8BIT_MODE) {
185 for (i = start; i <= (start + 3); i++) {
186 s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
187 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
188 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
192 for (i = 0; i < 3; i++) {
194 * MMC0 is intended to be used for eMMC. The
195 * card detect pin is used as a VDDEN signal to
196 * power on the eMMC. The 5420 iROM makes
197 * this same assumption.
199 if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
200 s5p_gpio_set_value(bank, i, 1);
201 s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
203 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
205 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
206 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
209 for (i = 3; i <= 6; i++) {
210 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
211 s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
212 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
218 static void exynos5_sromc_config(int flags)
220 struct exynos5_gpio_part1 *gpio1 =
221 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
227 * GPY0[0] SROM_CSn[0]
228 * GPY0[1] SROM_CSn[1](2)
229 * GPY0[2] SROM_CSn[2]
230 * GPY0[3] SROM_CSn[3]
234 * GPY1[0] EBI_BEn[0](2)
235 * GPY1[1] EBI_BEn[1](2)
236 * GPY1[2] SROM_WAIT(2)
237 * GPY1[3] EBI_DATA_RDn(2)
239 s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
241 s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
242 s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
244 for (i = 0; i < 4; i++)
245 s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
248 * EBI: 8 Addrss Lines
250 * GPY3[0] EBI_ADDR[0](2)
251 * GPY3[1] EBI_ADDR[1](2)
252 * GPY3[2] EBI_ADDR[2](2)
253 * GPY3[3] EBI_ADDR[3](2)
254 * GPY3[4] EBI_ADDR[4](2)
255 * GPY3[5] EBI_ADDR[5](2)
256 * GPY3[6] EBI_ADDR[6](2)
257 * GPY3[7] EBI_ADDR[7](2)
261 * GPY5[0] EBI_DATA[0](2)
262 * GPY5[1] EBI_DATA[1](2)
263 * GPY5[2] EBI_DATA[2](2)
264 * GPY5[3] EBI_DATA[3](2)
265 * GPY5[4] EBI_DATA[4](2)
266 * GPY5[5] EBI_DATA[5](2)
267 * GPY5[6] EBI_DATA[6](2)
268 * GPY5[7] EBI_DATA[7](2)
270 * GPY6[0] EBI_DATA[8](2)
271 * GPY6[1] EBI_DATA[9](2)
272 * GPY6[2] EBI_DATA[10](2)
273 * GPY6[3] EBI_DATA[11](2)
274 * GPY6[4] EBI_DATA[12](2)
275 * GPY6[5] EBI_DATA[13](2)
276 * GPY6[6] EBI_DATA[14](2)
277 * GPY6[7] EBI_DATA[15](2)
279 for (i = 0; i < 8; i++) {
280 s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
281 s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
283 s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
284 s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
286 s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
287 s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
291 static void exynos5_i2c_config(int peripheral, int flags)
294 struct exynos5_gpio_part1 *gpio1 =
295 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
297 switch (peripheral) {
299 s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
300 s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
303 s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
304 s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
307 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
308 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
311 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
312 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
315 s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
316 s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
319 s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
320 s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
323 s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
324 s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
327 s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
328 s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
333 static void exynos5420_i2c_config(int peripheral)
335 struct exynos5420_gpio_part1 *gpio1 =
336 (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
338 switch (peripheral) {
340 s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
341 s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
344 s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
345 s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
348 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
349 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
352 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
353 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
356 s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
357 s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
360 s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
361 s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
364 s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
365 s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
368 s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
369 s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
372 s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
373 s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
376 s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
377 s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
379 case PERIPH_ID_I2C10:
380 s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
381 s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
386 static void exynos5_i2s_config(int peripheral)
389 struct exynos5_gpio_part1 *gpio1 =
390 (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
391 struct exynos5_gpio_part4 *gpio4 =
392 (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
394 switch (peripheral) {
396 for (i = 0; i < 5; i++)
397 s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
400 for (i = 0; i < 5; i++)
401 s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
406 void exynos5_spi_config(int peripheral)
408 int cfg = 0, pin = 0, i;
409 struct s5p_gpio_bank *bank = NULL;
410 struct exynos5_gpio_part1 *gpio1 =
411 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
412 struct exynos5_gpio_part2 *gpio2 =
413 (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
415 switch (peripheral) {
418 cfg = GPIO_FUNC(0x2);
423 cfg = GPIO_FUNC(0x2);
428 cfg = GPIO_FUNC(0x5);
433 cfg = GPIO_FUNC(0x2);
437 for (i = 0; i < 2; i++) {
438 s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
439 s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
443 if (peripheral != PERIPH_ID_SPI4) {
444 for (i = pin; i < pin + 4; i++)
445 s5p_gpio_cfg_pin(bank, i, cfg);
449 void exynos5420_spi_config(int peripheral)
452 struct s5p_gpio_bank *bank = NULL;
453 struct exynos5420_gpio_part1 *gpio1 =
454 (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
455 struct exynos5420_gpio_part4 *gpio4 =
456 (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
458 switch (peripheral) {
461 cfg = GPIO_FUNC(0x2);
466 cfg = GPIO_FUNC(0x2);
471 cfg = GPIO_FUNC(0x5);
476 cfg = GPIO_FUNC(0x2);
486 debug("%s: invalid peripheral %d", __func__, peripheral);
490 if (peripheral != PERIPH_ID_SPI4) {
491 for (i = pin; i < pin + 4; i++)
492 s5p_gpio_cfg_pin(bank, i, cfg);
494 for (i = 0; i < 2; i++) {
495 s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
496 s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
501 static int exynos5_pinmux_config(int peripheral, int flags)
503 switch (peripheral) {
504 case PERIPH_ID_UART0:
505 case PERIPH_ID_UART1:
506 case PERIPH_ID_UART2:
507 case PERIPH_ID_UART3:
508 exynos5_uart_config(peripheral);
510 case PERIPH_ID_SDMMC0:
511 case PERIPH_ID_SDMMC1:
512 case PERIPH_ID_SDMMC2:
513 case PERIPH_ID_SDMMC3:
514 return exynos5_mmc_config(peripheral, flags);
515 case PERIPH_ID_SROMC:
516 exynos5_sromc_config(flags);
526 exynos5_i2c_config(peripheral, flags);
530 exynos5_i2s_config(peripheral);
537 exynos5_spi_config(peripheral);
540 debug("%s: invalid peripheral %d", __func__, peripheral);
547 static int exynos5420_pinmux_config(int peripheral, int flags)
549 switch (peripheral) {
550 case PERIPH_ID_UART0:
551 case PERIPH_ID_UART1:
552 case PERIPH_ID_UART2:
553 case PERIPH_ID_UART3:
554 exynos5420_uart_config(peripheral);
556 case PERIPH_ID_SDMMC0:
557 case PERIPH_ID_SDMMC1:
558 case PERIPH_ID_SDMMC2:
559 case PERIPH_ID_SDMMC3:
560 return exynos5420_mmc_config(peripheral, flags);
566 exynos5420_spi_config(peripheral);
578 case PERIPH_ID_I2C10:
579 exynos5420_i2c_config(peripheral);
582 debug("%s: invalid peripheral %d", __func__, peripheral);
589 static void exynos4_i2c_config(int peripheral, int flags)
591 struct exynos4_gpio_part1 *gpio1 =
592 (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
594 switch (peripheral) {
596 s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
597 s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
600 s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
601 s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
604 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
605 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
608 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
609 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
612 s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
613 s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
616 s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
617 s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
620 s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
621 s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
624 s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
625 s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
630 static int exynos4_mmc_config(int peripheral, int flags)
632 struct exynos4_gpio_part2 *gpio2 =
633 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
634 struct s5p_gpio_bank *bank, *bank_ext;
637 switch (peripheral) {
638 case PERIPH_ID_SDMMC0:
640 bank_ext = &gpio2->k1;
642 case PERIPH_ID_SDMMC2:
644 bank_ext = &gpio2->k3;
649 for (i = 0; i < 7; i++) {
652 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
653 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
654 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
656 if (flags & PINMUX_FLAG_8BIT_MODE) {
657 for (i = 3; i < 7; i++) {
658 s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
659 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
660 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
667 static void exynos4_uart_config(int peripheral)
669 struct exynos4_gpio_part1 *gpio1 =
670 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
671 struct s5p_gpio_bank *bank;
674 switch (peripheral) {
675 case PERIPH_ID_UART0:
680 case PERIPH_ID_UART1:
685 case PERIPH_ID_UART2:
690 case PERIPH_ID_UART3:
696 debug("%s: invalid peripheral %d", __func__, peripheral);
699 for (i = start; i < start + count; i++) {
700 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
701 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
704 static int exynos4_pinmux_config(int peripheral, int flags)
706 switch (peripheral) {
707 case PERIPH_ID_UART0:
708 case PERIPH_ID_UART1:
709 case PERIPH_ID_UART2:
710 case PERIPH_ID_UART3:
711 exynos4_uart_config(peripheral);
721 exynos4_i2c_config(peripheral, flags);
723 case PERIPH_ID_SDMMC0:
724 case PERIPH_ID_SDMMC2:
725 return exynos4_mmc_config(peripheral, flags);
726 case PERIPH_ID_SDMMC1:
727 case PERIPH_ID_SDMMC3:
728 case PERIPH_ID_SDMMC4:
729 debug("SDMMC device %d not implemented\n", peripheral);
732 debug("%s: invalid peripheral %d", __func__, peripheral);
739 int exynos_pinmux_config(int peripheral, int flags)
741 if (cpu_is_exynos5()) {
742 if (proid_is_exynos5420())
743 return exynos5420_pinmux_config(peripheral, flags);
744 else if (proid_is_exynos5250())
745 return exynos5_pinmux_config(peripheral, flags);
746 } else if (cpu_is_exynos4()) {
747 return exynos4_pinmux_config(peripheral, flags);
749 debug("pinmux functionality not supported\n");
755 #ifdef CONFIG_OF_CONTROL
756 static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
761 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
764 debug(" invalid peripheral id\n");
765 return PERIPH_ID_NONE;
771 static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
776 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
779 return PERIPH_ID_NONE;
784 int pinmux_decode_periph_id(const void *blob, int node)
786 if (cpu_is_exynos5())
787 return exynos5_pinmux_decode_periph_id(blob, node);
788 else if (cpu_is_exynos4())
789 return exynos4_pinmux_decode_periph_id(blob, node);
791 return PERIPH_ID_NONE;