2 * Copyright (c) 2012 Samsung Electronics.
3 * Abhilash Kesavan <a.kesavan@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/pinmux.h>
28 #include <asm/arch/sromc.h>
30 static void exynos5_uart_config(int peripheral)
32 struct exynos5_gpio_part1 *gpio1 =
33 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
34 struct s5p_gpio_bank *bank;
59 for (i = start; i < start + count; i++) {
60 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
61 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
65 static int exynos5_mmc_config(int peripheral, int flags)
67 struct exynos5_gpio_part1 *gpio1 =
68 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
69 struct s5p_gpio_bank *bank, *bank_ext;
70 int i, start = 0, gpio_func = 0;
73 case PERIPH_ID_SDMMC0:
75 bank_ext = &gpio1->c1;
77 gpio_func = GPIO_FUNC(0x2);
79 case PERIPH_ID_SDMMC1:
83 case PERIPH_ID_SDMMC2:
85 bank_ext = &gpio1->c4;
87 gpio_func = GPIO_FUNC(0x3);
89 case PERIPH_ID_SDMMC3:
94 if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
95 debug("SDMMC device %d does not support 8bit mode",
99 if (flags & PINMUX_FLAG_8BIT_MODE) {
100 for (i = start; i <= (start + 3); i++) {
101 s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
102 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
103 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
106 for (i = 0; i < 2; i++) {
107 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
108 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
109 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
111 for (i = 3; i <= 6; i++) {
112 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
113 s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
114 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
120 static void exynos5_sromc_config(int flags)
122 struct exynos5_gpio_part1 *gpio1 =
123 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
129 * GPY0[0] SROM_CSn[0]
130 * GPY0[1] SROM_CSn[1](2)
131 * GPY0[2] SROM_CSn[2]
132 * GPY0[3] SROM_CSn[3]
136 * GPY1[0] EBI_BEn[0](2)
137 * GPY1[1] EBI_BEn[1](2)
138 * GPY1[2] SROM_WAIT(2)
139 * GPY1[3] EBI_DATA_RDn(2)
141 s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
143 s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
144 s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
146 for (i = 0; i < 4; i++)
147 s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
150 * EBI: 8 Addrss Lines
152 * GPY3[0] EBI_ADDR[0](2)
153 * GPY3[1] EBI_ADDR[1](2)
154 * GPY3[2] EBI_ADDR[2](2)
155 * GPY3[3] EBI_ADDR[3](2)
156 * GPY3[4] EBI_ADDR[4](2)
157 * GPY3[5] EBI_ADDR[5](2)
158 * GPY3[6] EBI_ADDR[6](2)
159 * GPY3[7] EBI_ADDR[7](2)
163 * GPY5[0] EBI_DATA[0](2)
164 * GPY5[1] EBI_DATA[1](2)
165 * GPY5[2] EBI_DATA[2](2)
166 * GPY5[3] EBI_DATA[3](2)
167 * GPY5[4] EBI_DATA[4](2)
168 * GPY5[5] EBI_DATA[5](2)
169 * GPY5[6] EBI_DATA[6](2)
170 * GPY5[7] EBI_DATA[7](2)
172 * GPY6[0] EBI_DATA[8](2)
173 * GPY6[1] EBI_DATA[9](2)
174 * GPY6[2] EBI_DATA[10](2)
175 * GPY6[3] EBI_DATA[11](2)
176 * GPY6[4] EBI_DATA[12](2)
177 * GPY6[5] EBI_DATA[13](2)
178 * GPY6[6] EBI_DATA[14](2)
179 * GPY6[7] EBI_DATA[15](2)
181 for (i = 0; i < 8; i++) {
182 s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
183 s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
185 s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
186 s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
188 s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
189 s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
193 static void exynos5_i2c_config(int peripheral, int flags)
196 struct exynos5_gpio_part1 *gpio1 =
197 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
199 switch (peripheral) {
201 s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
202 s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
205 s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
206 s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
209 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
210 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
213 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
214 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
217 s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
218 s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
221 s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
222 s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
225 s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
226 s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
229 s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
230 s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
235 static void exynos5_i2s_config(int peripheral)
238 struct exynos5_gpio_part1 *gpio1 =
239 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
241 for (i = 0; i < 5; i++)
242 s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
245 void exynos5_spi_config(int peripheral)
247 int cfg = 0, pin = 0, i;
248 struct s5p_gpio_bank *bank = NULL;
249 struct exynos5_gpio_part1 *gpio1 =
250 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
251 struct exynos5_gpio_part2 *gpio2 =
252 (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
254 switch (peripheral) {
257 cfg = GPIO_FUNC(0x2);
262 cfg = GPIO_FUNC(0x2);
267 cfg = GPIO_FUNC(0x5);
272 cfg = GPIO_FUNC(0x2);
276 for (i = 0; i < 2; i++) {
277 s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
278 s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
282 if (peripheral != PERIPH_ID_SPI4) {
283 for (i = pin; i < pin + 4; i++)
284 s5p_gpio_cfg_pin(bank, i, cfg);
288 static int exynos5_pinmux_config(int peripheral, int flags)
290 switch (peripheral) {
291 case PERIPH_ID_UART0:
292 case PERIPH_ID_UART1:
293 case PERIPH_ID_UART2:
294 case PERIPH_ID_UART3:
295 exynos5_uart_config(peripheral);
297 case PERIPH_ID_SDMMC0:
298 case PERIPH_ID_SDMMC1:
299 case PERIPH_ID_SDMMC2:
300 case PERIPH_ID_SDMMC3:
301 return exynos5_mmc_config(peripheral, flags);
302 case PERIPH_ID_SROMC:
303 exynos5_sromc_config(flags);
313 exynos5_i2c_config(peripheral, flags);
316 exynos5_i2s_config(peripheral);
323 exynos5_spi_config(peripheral);
326 debug("%s: invalid peripheral %d", __func__, peripheral);
333 static void exynos4_i2c_config(int peripheral, int flags)
335 struct exynos4_gpio_part1 *gpio1 =
336 (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
338 switch (peripheral) {
340 s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
341 s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
344 s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
345 s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
348 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
349 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
352 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
353 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
356 s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
357 s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
360 s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
361 s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
364 s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
365 s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
368 s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
369 s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
374 static int exynos4_mmc_config(int peripheral, int flags)
376 struct exynos4_gpio_part2 *gpio2 =
377 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
378 struct s5p_gpio_bank *bank, *bank_ext;
381 switch (peripheral) {
382 case PERIPH_ID_SDMMC0:
384 bank_ext = &gpio2->k1;
386 case PERIPH_ID_SDMMC2:
388 bank_ext = &gpio2->k3;
393 for (i = 0; i < 7; i++) {
396 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
397 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
398 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
400 if (flags & PINMUX_FLAG_8BIT_MODE) {
401 for (i = 3; i < 7; i++) {
402 s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
403 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
404 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
411 static int exynos4_pinmux_config(int peripheral, int flags)
413 switch (peripheral) {
422 exynos4_i2c_config(peripheral, flags);
424 case PERIPH_ID_SDMMC0:
425 case PERIPH_ID_SDMMC2:
426 return exynos4_mmc_config(peripheral, flags);
427 case PERIPH_ID_SDMMC1:
428 case PERIPH_ID_SDMMC3:
429 case PERIPH_ID_SDMMC4:
430 printf("SDMMC device %d not implemented\n", peripheral);
433 debug("%s: invalid peripheral %d", __func__, peripheral);
440 int exynos_pinmux_config(int peripheral, int flags)
442 if (cpu_is_exynos5())
443 return exynos5_pinmux_config(peripheral, flags);
444 else if (cpu_is_exynos4())
445 return exynos4_pinmux_config(peripheral, flags);
447 debug("pinmux functionality not supported\n");
452 #ifdef CONFIG_OF_CONTROL
453 static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
458 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
461 return PERIPH_ID_NONE;
463 /* check for invalid peripheral id */
464 if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
467 debug(" invalid peripheral id\n");
468 return PERIPH_ID_NONE;
471 int pinmux_decode_periph_id(const void *blob, int node)
473 if (cpu_is_exynos5())
474 return exynos5_pinmux_decode_periph_id(blob, node);
476 return PERIPH_ID_NONE;