2 * Copyright (c) 2012 Samsung Electronics.
3 * Abhilash Kesavan <a.kesavan@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/pinmux.h>
27 #include <asm/arch/sromc.h>
29 static void exynos5_uart_config(int peripheral)
31 struct exynos5_gpio_part1 *gpio1 =
32 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
33 struct s5p_gpio_bank *bank;
58 for (i = start; i < start + count; i++) {
59 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
60 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
64 static int exynos5_mmc_config(int peripheral, int flags)
66 struct exynos5_gpio_part1 *gpio1 =
67 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
68 struct s5p_gpio_bank *bank, *bank_ext;
72 case PERIPH_ID_SDMMC0:
74 bank_ext = &gpio1->c1;
76 case PERIPH_ID_SDMMC1:
80 case PERIPH_ID_SDMMC2:
82 bank_ext = &gpio1->c3;
84 case PERIPH_ID_SDMMC3:
89 if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
90 debug("SDMMC device %d does not support 8bit mode",
94 if (flags & PINMUX_FLAG_8BIT_MODE) {
95 for (i = 3; i <= 6; i++) {
96 s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
97 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
98 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
101 for (i = 0; i < 2; i++) {
102 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
103 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
104 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
106 for (i = 3; i <= 6; i++) {
107 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
108 s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
109 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
114 static void exynos5_sromc_config(int flags)
116 struct exynos5_gpio_part1 *gpio1 =
117 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
123 * GPY0[0] SROM_CSn[0]
124 * GPY0[1] SROM_CSn[1](2)
125 * GPY0[2] SROM_CSn[2]
126 * GPY0[3] SROM_CSn[3]
130 * GPY1[0] EBI_BEn[0](2)
131 * GPY1[1] EBI_BEn[1](2)
132 * GPY1[2] SROM_WAIT(2)
133 * GPY1[3] EBI_DATA_RDn(2)
135 s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
137 s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
138 s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
140 for (i = 0; i < 4; i++)
141 s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
144 * EBI: 8 Addrss Lines
146 * GPY3[0] EBI_ADDR[0](2)
147 * GPY3[1] EBI_ADDR[1](2)
148 * GPY3[2] EBI_ADDR[2](2)
149 * GPY3[3] EBI_ADDR[3](2)
150 * GPY3[4] EBI_ADDR[4](2)
151 * GPY3[5] EBI_ADDR[5](2)
152 * GPY3[6] EBI_ADDR[6](2)
153 * GPY3[7] EBI_ADDR[7](2)
157 * GPY5[0] EBI_DATA[0](2)
158 * GPY5[1] EBI_DATA[1](2)
159 * GPY5[2] EBI_DATA[2](2)
160 * GPY5[3] EBI_DATA[3](2)
161 * GPY5[4] EBI_DATA[4](2)
162 * GPY5[5] EBI_DATA[5](2)
163 * GPY5[6] EBI_DATA[6](2)
164 * GPY5[7] EBI_DATA[7](2)
166 * GPY6[0] EBI_DATA[8](2)
167 * GPY6[1] EBI_DATA[9](2)
168 * GPY6[2] EBI_DATA[10](2)
169 * GPY6[3] EBI_DATA[11](2)
170 * GPY6[4] EBI_DATA[12](2)
171 * GPY6[5] EBI_DATA[13](2)
172 * GPY6[6] EBI_DATA[14](2)
173 * GPY6[7] EBI_DATA[15](2)
175 for (i = 0; i < 8; i++) {
176 s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
177 s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
179 s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
180 s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
182 s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
183 s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
187 static int exynos5_pinmux_config(int peripheral, int flags)
189 switch (peripheral) {
190 case PERIPH_ID_UART0:
191 case PERIPH_ID_UART1:
192 case PERIPH_ID_UART2:
193 case PERIPH_ID_UART3:
194 exynos5_uart_config(peripheral);
196 case PERIPH_ID_SDMMC0:
197 case PERIPH_ID_SDMMC1:
198 case PERIPH_ID_SDMMC2:
199 case PERIPH_ID_SDMMC3:
200 return exynos5_mmc_config(peripheral, flags);
201 case PERIPH_ID_SROMC:
202 exynos5_sromc_config(flags);
205 debug("%s: invalid peripheral %d", __func__, peripheral);
212 int exynos_pinmux_config(int peripheral, int flags)
214 if (cpu_is_exynos5())
215 return exynos5_pinmux_config(peripheral, flags);
217 debug("pinmux functionality not supported\n");