2 * Copyright (c) 2012 Samsung Electronics.
3 * Abhilash Kesavan <a.kesavan@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/gpio.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/sromc.h>
14 static void exynos5_uart_config(int peripheral)
16 struct exynos5_gpio_part1 *gpio1 =
17 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
18 struct s5p_gpio_bank *bank;
43 for (i = start; i < start + count; i++) {
44 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
45 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
49 static int exynos5_mmc_config(int peripheral, int flags)
51 struct exynos5_gpio_part1 *gpio1 =
52 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
53 struct s5p_gpio_bank *bank, *bank_ext;
54 int i, start = 0, gpio_func = 0;
57 case PERIPH_ID_SDMMC0:
59 bank_ext = &gpio1->c1;
61 gpio_func = GPIO_FUNC(0x2);
63 case PERIPH_ID_SDMMC1:
67 case PERIPH_ID_SDMMC2:
69 bank_ext = &gpio1->c4;
71 gpio_func = GPIO_FUNC(0x3);
73 case PERIPH_ID_SDMMC3:
78 if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
79 debug("SDMMC device %d does not support 8bit mode",
83 if (flags & PINMUX_FLAG_8BIT_MODE) {
84 for (i = start; i <= (start + 3); i++) {
85 s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
86 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
87 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
90 for (i = 0; i < 2; i++) {
91 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
92 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
93 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
95 for (i = 3; i <= 6; i++) {
96 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
97 s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
98 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
104 static void exynos5_sromc_config(int flags)
106 struct exynos5_gpio_part1 *gpio1 =
107 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
113 * GPY0[0] SROM_CSn[0]
114 * GPY0[1] SROM_CSn[1](2)
115 * GPY0[2] SROM_CSn[2]
116 * GPY0[3] SROM_CSn[3]
120 * GPY1[0] EBI_BEn[0](2)
121 * GPY1[1] EBI_BEn[1](2)
122 * GPY1[2] SROM_WAIT(2)
123 * GPY1[3] EBI_DATA_RDn(2)
125 s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
127 s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
128 s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
130 for (i = 0; i < 4; i++)
131 s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
134 * EBI: 8 Addrss Lines
136 * GPY3[0] EBI_ADDR[0](2)
137 * GPY3[1] EBI_ADDR[1](2)
138 * GPY3[2] EBI_ADDR[2](2)
139 * GPY3[3] EBI_ADDR[3](2)
140 * GPY3[4] EBI_ADDR[4](2)
141 * GPY3[5] EBI_ADDR[5](2)
142 * GPY3[6] EBI_ADDR[6](2)
143 * GPY3[7] EBI_ADDR[7](2)
147 * GPY5[0] EBI_DATA[0](2)
148 * GPY5[1] EBI_DATA[1](2)
149 * GPY5[2] EBI_DATA[2](2)
150 * GPY5[3] EBI_DATA[3](2)
151 * GPY5[4] EBI_DATA[4](2)
152 * GPY5[5] EBI_DATA[5](2)
153 * GPY5[6] EBI_DATA[6](2)
154 * GPY5[7] EBI_DATA[7](2)
156 * GPY6[0] EBI_DATA[8](2)
157 * GPY6[1] EBI_DATA[9](2)
158 * GPY6[2] EBI_DATA[10](2)
159 * GPY6[3] EBI_DATA[11](2)
160 * GPY6[4] EBI_DATA[12](2)
161 * GPY6[5] EBI_DATA[13](2)
162 * GPY6[6] EBI_DATA[14](2)
163 * GPY6[7] EBI_DATA[15](2)
165 for (i = 0; i < 8; i++) {
166 s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
167 s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
169 s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
170 s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
172 s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
173 s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
177 static void exynos5_i2c_config(int peripheral, int flags)
180 struct exynos5_gpio_part1 *gpio1 =
181 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
183 switch (peripheral) {
185 s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
186 s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
189 s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
190 s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
193 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
194 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
197 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
198 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
201 s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
202 s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
205 s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
206 s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
209 s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
210 s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
213 s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
214 s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
219 static void exynos5_i2s_config(int peripheral)
222 struct exynos5_gpio_part1 *gpio1 =
223 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
225 for (i = 0; i < 5; i++)
226 s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
229 void exynos5_spi_config(int peripheral)
231 int cfg = 0, pin = 0, i;
232 struct s5p_gpio_bank *bank = NULL;
233 struct exynos5_gpio_part1 *gpio1 =
234 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
235 struct exynos5_gpio_part2 *gpio2 =
236 (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
238 switch (peripheral) {
241 cfg = GPIO_FUNC(0x2);
246 cfg = GPIO_FUNC(0x2);
251 cfg = GPIO_FUNC(0x5);
256 cfg = GPIO_FUNC(0x2);
260 for (i = 0; i < 2; i++) {
261 s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
262 s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
266 if (peripheral != PERIPH_ID_SPI4) {
267 for (i = pin; i < pin + 4; i++)
268 s5p_gpio_cfg_pin(bank, i, cfg);
272 static int exynos5_pinmux_config(int peripheral, int flags)
274 switch (peripheral) {
275 case PERIPH_ID_UART0:
276 case PERIPH_ID_UART1:
277 case PERIPH_ID_UART2:
278 case PERIPH_ID_UART3:
279 exynos5_uart_config(peripheral);
281 case PERIPH_ID_SDMMC0:
282 case PERIPH_ID_SDMMC1:
283 case PERIPH_ID_SDMMC2:
284 case PERIPH_ID_SDMMC3:
285 return exynos5_mmc_config(peripheral, flags);
286 case PERIPH_ID_SROMC:
287 exynos5_sromc_config(flags);
297 exynos5_i2c_config(peripheral, flags);
300 exynos5_i2s_config(peripheral);
307 exynos5_spi_config(peripheral);
310 debug("%s: invalid peripheral %d", __func__, peripheral);
317 static void exynos4_i2c_config(int peripheral, int flags)
319 struct exynos4_gpio_part1 *gpio1 =
320 (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
322 switch (peripheral) {
324 s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
325 s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
328 s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
329 s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
332 s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
333 s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
336 s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
337 s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
340 s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
341 s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
344 s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
345 s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
348 s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
349 s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
352 s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
353 s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
358 static int exynos4_mmc_config(int peripheral, int flags)
360 struct exynos4_gpio_part2 *gpio2 =
361 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
362 struct s5p_gpio_bank *bank, *bank_ext;
365 switch (peripheral) {
366 case PERIPH_ID_SDMMC0:
368 bank_ext = &gpio2->k1;
370 case PERIPH_ID_SDMMC2:
372 bank_ext = &gpio2->k3;
377 for (i = 0; i < 7; i++) {
380 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
381 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
382 s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
384 if (flags & PINMUX_FLAG_8BIT_MODE) {
385 for (i = 3; i < 7; i++) {
386 s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
387 s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
388 s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
395 static void exynos4_uart_config(int peripheral)
397 struct exynos4_gpio_part1 *gpio1 =
398 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
399 struct s5p_gpio_bank *bank;
402 switch (peripheral) {
403 case PERIPH_ID_UART0:
408 case PERIPH_ID_UART1:
413 case PERIPH_ID_UART2:
418 case PERIPH_ID_UART3:
424 for (i = start; i < start + count; i++) {
425 s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
426 s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
429 static int exynos4_pinmux_config(int peripheral, int flags)
431 switch (peripheral) {
432 case PERIPH_ID_UART0:
433 case PERIPH_ID_UART1:
434 case PERIPH_ID_UART2:
435 case PERIPH_ID_UART3:
436 exynos4_uart_config(peripheral);
446 exynos4_i2c_config(peripheral, flags);
448 case PERIPH_ID_SDMMC0:
449 case PERIPH_ID_SDMMC2:
450 return exynos4_mmc_config(peripheral, flags);
451 case PERIPH_ID_SDMMC1:
452 case PERIPH_ID_SDMMC3:
453 case PERIPH_ID_SDMMC4:
454 printf("SDMMC device %d not implemented\n", peripheral);
457 debug("%s: invalid peripheral %d", __func__, peripheral);
464 int exynos_pinmux_config(int peripheral, int flags)
466 if (cpu_is_exynos5())
467 return exynos5_pinmux_config(peripheral, flags);
468 else if (cpu_is_exynos4())
469 return exynos4_pinmux_config(peripheral, flags);
471 debug("pinmux functionality not supported\n");
476 #ifdef CONFIG_OF_CONTROL
477 static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
482 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
485 return PERIPH_ID_NONE;
487 /* check for invalid peripheral id */
488 if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
491 debug(" invalid peripheral id\n");
492 return PERIPH_ID_NONE;
495 int pinmux_decode_periph_id(const void *blob, int node)
497 if (cpu_is_exynos5())
498 return exynos5_pinmux_decode_periph_id(blob, node);
500 return PERIPH_ID_NONE;