2 * Copyright (C) 2012 Samsung Electronics
3 * Donghwa Lee <dh09.lee@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/power.h>
12 static void exynos4_mipi_phy_control(unsigned int dev_index,
15 struct exynos4_power *pmu =
16 (struct exynos4_power *)samsung_get_base_power();
17 unsigned int addr, cfg = 0;
20 addr = (unsigned int)&pmu->mipi_phy0_control;
22 addr = (unsigned int)&pmu->mipi_phy1_control;
27 cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
29 cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
34 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
37 exynos4_mipi_phy_control(dev_index, enable);
40 void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
42 struct exynos5_power *power =
43 (struct exynos5_power *)samsung_get_base_power();
46 /* Enabling USBHOST_PHY */
47 setbits_le32(&power->usbhost_phy_control,
48 POWER_USB_HOST_PHY_CTRL_EN);
50 /* Disabling USBHOST_PHY */
51 clrbits_le32(&power->usbhost_phy_control,
52 POWER_USB_HOST_PHY_CTRL_EN);
56 void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
58 struct exynos4412_power *power =
59 (struct exynos4412_power *)samsung_get_base_power();
62 /* Enabling USBHOST_PHY */
63 setbits_le32(&power->usbhost_phy_control,
64 POWER_USB_HOST_PHY_CTRL_EN);
65 setbits_le32(&power->hsic1_phy_control,
66 POWER_USB_HOST_PHY_CTRL_EN);
67 setbits_le32(&power->hsic2_phy_control,
68 POWER_USB_HOST_PHY_CTRL_EN);
70 /* Disabling USBHOST_PHY */
71 clrbits_le32(&power->usbhost_phy_control,
72 POWER_USB_HOST_PHY_CTRL_EN);
73 clrbits_le32(&power->hsic1_phy_control,
74 POWER_USB_HOST_PHY_CTRL_EN);
75 clrbits_le32(&power->hsic2_phy_control,
76 POWER_USB_HOST_PHY_CTRL_EN);
80 void set_usbhost_phy_ctrl(unsigned int enable)
83 exynos5_set_usbhost_phy_ctrl(enable);
84 else if (cpu_is_exynos4())
85 if (proid_is_exynos4412())
86 exynos4412_set_usbhost_phy_ctrl(enable);
89 static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
91 struct exynos5_power *power =
92 (struct exynos5_power *)samsung_get_base_power();
95 /* Enabling USBDRD_PHY */
96 setbits_le32(&power->usbdrd_phy_control,
97 POWER_USB_DRD_PHY_CTRL_EN);
99 /* Disabling USBDRD_PHY */
100 clrbits_le32(&power->usbdrd_phy_control,
101 POWER_USB_DRD_PHY_CTRL_EN);
105 void set_usbdrd_phy_ctrl(unsigned int enable)
107 if (cpu_is_exynos5())
108 exynos5_set_usbdrd_phy_ctrl(enable);
111 static void exynos5_dp_phy_control(unsigned int enable)
114 struct exynos5_power *power =
115 (struct exynos5_power *)samsung_get_base_power();
117 cfg = readl(&power->dptx_phy_control);
119 cfg |= EXYNOS_DP_PHY_ENABLE;
121 cfg &= ~EXYNOS_DP_PHY_ENABLE;
123 writel(cfg, &power->dptx_phy_control);
126 void set_dp_phy_ctrl(unsigned int enable)
128 if (cpu_is_exynos5())
129 exynos5_dp_phy_control(enable);
132 static void exynos5_set_ps_hold_ctrl(void)
134 struct exynos5_power *power =
135 (struct exynos5_power *)samsung_get_base_power();
137 /* Set PS-Hold high */
138 setbits_le32(&power->ps_hold_control,
139 EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
143 * Set ps_hold data driving value high
144 * This enables the machine to stay powered on
145 * after the initial power-on condition goes away
146 * (e.g. power button).
148 void set_ps_hold_ctrl(void)
150 if (cpu_is_exynos5())
151 exynos5_set_ps_hold_ctrl();
155 static void exynos5_set_xclkout(void)
157 struct exynos5_power *power =
158 (struct exynos5_power *)samsung_get_base_power();
160 /* use xxti for xclk out */
161 clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
165 void set_xclkout(void)
167 if (cpu_is_exynos5())
168 exynos5_set_xclkout();
171 /* Enables hardware tripping to power off the system when TMU fails */
172 void set_hw_thermal_trip(void)
174 if (cpu_is_exynos5()) {
175 struct exynos5_power *power =
176 (struct exynos5_power *)samsung_get_base_power();
178 /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
179 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
183 static uint32_t exynos5_get_reset_status(void)
185 struct exynos5_power *power =
186 (struct exynos5_power *)samsung_get_base_power();
188 return power->inform1;
191 static uint32_t exynos4_get_reset_status(void)
193 struct exynos4_power *power =
194 (struct exynos4_power *)samsung_get_base_power();
196 return power->inform1;
199 uint32_t get_reset_status(void)
201 if (cpu_is_exynos5())
202 return exynos5_get_reset_status();
204 return exynos4_get_reset_status();
207 static void exynos5_power_exit_wakeup(void)
209 struct exynos5_power *power =
210 (struct exynos5_power *)samsung_get_base_power();
211 typedef void (*resume_func)(void);
213 ((resume_func)power->inform0)();
216 static void exynos4_power_exit_wakeup(void)
218 struct exynos4_power *power =
219 (struct exynos4_power *)samsung_get_base_power();
220 typedef void (*resume_func)(void);
222 ((resume_func)power->inform0)();
225 void power_exit_wakeup(void)
227 if (cpu_is_exynos5())
228 exynos5_power_exit_wakeup();
230 exynos4_power_exit_wakeup();
233 unsigned int get_boot_mode(void)
235 unsigned int om_pin = samsung_get_base_power();
237 return readl(om_pin) & OM_PIN_MASK;