2 * Copyright 2014 Broadcom Corporation.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/iproc-common/armpll.h>
10 #include <asm/iproc-common/sysmap.h>
12 #define NELEMS(x) (sizeof(x) / sizeof(x[0]))
14 struct armpll_parameters {
16 unsigned int ndiv_int;
17 unsigned int ndiv_frac;
22 struct armpll_parameters armpll_clk_tab[] = {
26 { 448, 71, 713050, 1, 6},
28 { 560, 89, 629145, 1, 6},
31 { 896, 71, 713050, 1, 7},
34 { 1120, 89, 629145, 1, 7},
38 uint32_t armpll_config(uint32_t clkmhz)
44 uint32_t timeout_countdown;
47 for (i = 0; i < NELEMS(armpll_clk_tab); i++) {
48 if (armpll_clk_tab[i].mode == clkmhz) {
55 printf("Error: Clock configuration not supported\n");
56 goto armpll_config_done;
59 /* Enable write access */
60 writel(IPROC_REG_WRITE_ACCESS, IHOST_PROC_CLK_WR_ACCESS);
67 /* Bypass ARM clock and run on sysclk */
68 writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
69 freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
70 freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
71 freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
72 freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
73 IHOST_PROC_CLK_POLICY_FREQ);
75 writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
76 1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
77 IHOST_PROC_CLK_POLICY_CTL);
79 /* Poll CCU until operation complete */
80 timeout_countdown = 0x100000;
81 while (readl(IHOST_PROC_CLK_POLICY_CTL) &
82 (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
84 if (timeout_countdown == 0) {
85 printf("CCU polling timedout\n");
87 goto armpll_config_done;
91 if (clkmhz == 25 || clkmhz == 100) {
93 goto armpll_config_done;
96 /* Now it is safe to program the PLL */
97 pll = readl(IHOST_PROC_CLK_PLLARMB);
98 pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1);
100 ((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1) &
101 (armpll_clk_tab[i].ndiv_frac <<
102 IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R);
104 writel(pll, IHOST_PROC_CLK_PLLARMB);
106 writel(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK |
107 armpll_clk_tab[i].ndiv_int <<
108 IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R |
109 armpll_clk_tab[i].pdiv <<
110 IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R |
111 1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB,
112 IHOST_PROC_CLK_PLLARMA);
114 /* Poll ARM PLL Lock until operation complete */
115 timeout_countdown = 0x100000;
116 while (readl(IHOST_PROC_CLK_PLLARMA) &
117 (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK)) {
119 if (timeout_countdown == 0) {
120 printf("ARM PLL lock failed\n");
122 goto armpll_config_done;
126 pll = readl(IHOST_PROC_CLK_PLLARMA);
127 pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB);
128 writel(pll, IHOST_PROC_CLK_PLLARMA);
131 writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
132 armpll_clk_tab[i].freqid <<
133 IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
134 armpll_clk_tab[i].freqid <<
135 IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
136 armpll_clk_tab[i].freqid <<
137 IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
138 armpll_clk_tab[i+4].freqid <<
139 IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
140 IHOST_PROC_CLK_POLICY_FREQ);
142 writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE0_CLKGATE);
143 writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE1_CLKGATE);
144 writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_SWITCH_CLKGATE);
145 writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_PERIPH_CLKGATE);
146 writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_APB0_CLKGATE);
148 writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
149 1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
150 IHOST_PROC_CLK_POLICY_CTL);
152 /* Poll CCU until operation complete */
153 timeout_countdown = 0x100000;
154 while (readl(IHOST_PROC_CLK_POLICY_CTL) &
155 (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
157 if (timeout_countdown == 0) {
158 printf("CCU polling failed\n");
160 goto armpll_config_done;
166 /* Disable access to PLL registers */
167 writel(0, IHOST_PROC_CLK_WR_ACCESS);