2 * Keystone2: get clk rate for K2E
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/clock_defs.h>
14 const struct keystone_pll_regs keystone_pll_regs[] = {
15 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
16 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
17 [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
21 * pll_freq_get - get pll frequency
22 * Fout = Fref * NF(mult) / NR(prediv) / OD
23 * @pll: pll identifier
25 static unsigned long pll_freq_get(int pll)
27 unsigned long mult = 1, prediv = 1, output_div = 2;
31 if (pll == CORE_PLL) {
32 ret = external_clk[sys_clk];
33 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
35 tmp = __raw_readl(KS2_MAINPLLCTL0);
36 prediv = (tmp & PLL_DIV_MASK) + 1;
37 mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
38 (pllctl_reg_read(pll, mult) &
39 PLLM_MULT_LO_MASK)) + 1;
40 output_div = ((pllctl_reg_read(pll, secctl) >>
41 PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
43 ret = ret / prediv / output_div * mult;
48 ret = external_clk[pa_clk];
49 reg = KS2_PASSPLLCTL0;
52 ret = external_clk[ddr3_clk];
53 reg = KS2_DDR3APLLCTL0;
59 tmp = __raw_readl(reg);
61 if (!(tmp & PLLCTL_BYPASS)) {
63 prediv = (tmp & PLL_DIV_MASK) + 1;
64 mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
65 output_div = ((tmp >> PLL_CLKOD_SHIFT) &
67 ret = ((ret / prediv) * mult) / output_div;
74 unsigned long clk_get_rate(unsigned int clk)
77 case core_pll_clk: return pll_freq_get(CORE_PLL);
78 case pass_pll_clk: return pll_freq_get(PASS_PLL);
79 case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
81 case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
82 case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
83 case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
84 case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
85 case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
86 case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
87 case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
88 case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
89 case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
90 case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
91 case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
92 case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
93 case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
94 case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
95 case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;