2 * Keystone2: get clk rate for K2HK
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/clock_defs.h>
14 const struct keystone_pll_regs keystone_pll_regs[] = {
15 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
16 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
17 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
18 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
19 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
55 * pll_freq_get - get pll frequency
56 * Fout = Fref * NF(mult) / NR(prediv) / OD
57 * @pll: pll identifier
59 static unsigned long pll_freq_get(int pll)
61 unsigned long mult = 1, prediv = 1, output_div = 2;
65 if (pll == CORE_PLL) {
66 ret = external_clk[sys_clk];
67 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
69 tmp = __raw_readl(KS2_MAINPLLCTL0);
70 prediv = (tmp & PLL_DIV_MASK) + 1;
71 mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
72 (pllctl_reg_read(pll, mult) &
73 PLLM_MULT_LO_MASK)) + 1;
74 output_div = ((pllctl_reg_read(pll, secctl) >>
75 PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
77 ret = ret / prediv / output_div * mult;
82 ret = external_clk[pa_clk];
83 reg = KS2_PASSPLLCTL0;
86 ret = external_clk[tetris_clk];
90 ret = external_clk[ddr3a_clk];
91 reg = KS2_DDR3APLLCTL0;
94 ret = external_clk[ddr3b_clk];
95 reg = KS2_DDR3BPLLCTL0;
101 tmp = __raw_readl(reg);
103 if (!(tmp & PLLCTL_BYPASS)) {
104 /* Bypass disabled */
105 prediv = (tmp & PLL_DIV_MASK) + 1;
106 mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
107 output_div = ((tmp >> PLL_CLKOD_SHIFT) &
109 ret = ((ret / prediv) * mult) / output_div;
116 unsigned long clk_get_rate(unsigned int clk)
119 case core_pll_clk: return pll_freq_get(CORE_PLL);
120 case pass_pll_clk: return pll_freq_get(PASS_PLL);
121 case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
122 case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
123 case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
125 case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
126 case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
127 case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
128 case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
129 case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
130 case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
131 case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
132 case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
133 case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
134 case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
135 case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
136 case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
137 case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
138 case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
139 case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;