2 * Keystone2: Architecture initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/msmc.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/hardware.h>
17 void chip_configuration_unlock(void)
19 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
20 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
23 int arch_cpu_init(void)
25 chip_configuration_unlock();
28 msmc_share_all_segments(8); /* TETRIS */
29 msmc_share_all_segments(9); /* NETCP */
30 msmc_share_all_segments(10); /* QM PDSP */
31 msmc_share_all_segments(11); /* PCIE 0 */
33 msmc_share_all_segments(13); /* PCIE 1 */
37 * just initialise the COM2 port so that TI specific
38 * UART register PWREMU_MGMT is initialized. Linux UART
39 * driver doesn't handle this.
41 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
42 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
47 void reset_cpu(ulong addr)
49 volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
52 tmp = *rstctrl & KS2_RSTCTRL_MASK;
53 *rstctrl = tmp | KS2_RSTCTRL_KEY;
55 *rstctrl &= KS2_RSTCTRL_SWRST;
61 void enable_caches(void)
63 #ifndef CONFIG_SYS_DCACHE_OFF
64 /* Enable D-cache. I-cache is already enabled in start.S */