3 select SYS_FSL_ERRATUM_A010315
7 select SYS_FSL_DDR_VER_50
9 select SYS_FSL_SEC_COMPAT_5
11 menu "LS102xA architecture"
12 depends on ARCH_LS1021A
16 depends on ARCH_LS1021A
19 int "Maximum number of CPUs permitted for LS102xA"
20 depends on ARCH_LS1021A
23 Set this number to the maximum number of possible CPUs in the SoC.
24 SoCs may have multiple clusters with each cluster may have multiple
25 ports. If some ports are reserved but higher ports are used for
26 cores, count the reserved ports. This will allocate enough memory
27 in spin table to properly handle all cores.
29 config NUM_DDR_CONTROLLERS
30 int "Maximum DDR controllers"
36 Enable Freescale Secure Boot feature. Normally selected
37 by defconfig. If unsure, do not change.
39 config SYS_FSL_ERRATUM_A010315
40 bool "Workaround for PCIe erratum A010315"
52 bool "Freescale DDR driver"
54 Select Freescale General DDR driver, shared between most Freescale
55 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
56 based Layerscape SoCs (such as ls2080a).
62 Access DDR registers in big-endian.
64 config SYS_FSL_DDR_VER
66 default 50 if SYS_FSL_DDR_VER_50
68 config SYS_FSL_DDR_VER_50
71 config SYS_FSL_DDRC_ARM_GEN3
74 config SYS_FSL_DDRC_GEN4
78 bool "Freescale DDR3 controller"
79 depends on !SYS_FSL_DDR4
81 select SYS_FSL_DDRC_ARM_GEN3
83 Enable Freescale DDR3 controller on ARM-based SoCs.
86 bool "Freescale DDR4 controller"
88 select SYS_FSL_DDRC_GEN4
90 Enable Freescale DDR4 controller.
92 config SYS_FSL_IFC_BANK_COUNT
93 int "Maximum banks of Integrated flash controller"
94 depends on ARCH_LS1021A