3 select SYS_FSL_ERRATUM_A010315
7 select SYS_FSL_DDR_VER_50
9 menu "LS102xA architecture"
10 depends on ARCH_LS1021A
14 depends on ARCH_LS1021A
17 int "Maximum number of CPUs permitted for LS102xA"
18 depends on ARCH_LS1021A
21 Set this number to the maximum number of possible CPUs in the SoC.
22 SoCs may have multiple clusters with each cluster may have multiple
23 ports. If some ports are reserved but higher ports are used for
24 cores, count the reserved ports. This will allocate enough memory
25 in spin table to properly handle all cores.
27 config NUM_DDR_CONTROLLERS
28 int "Maximum DDR controllers"
31 config SYS_FSL_ERRATUM_A010315
32 bool "Workaround for PCIe erratum A010315"
44 bool "Freescale DDR driver"
46 Select Freescale General DDR driver, shared between most Freescale
47 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
48 based Layerscape SoCs (such as ls2080a).
54 Access DDR registers in big-endian.
56 config SYS_FSL_DDR_VER
58 default 50 if SYS_FSL_DDR_VER_50
60 config SYS_FSL_DDR_VER_50
63 config SYS_FSL_DDRC_ARM_GEN3
66 config SYS_FSL_DDRC_GEN4
70 bool "Freescale DDR3 controller"
71 depends on !SYS_FSL_DDR4
73 select SYS_FSL_DDRC_ARM_GEN3
75 Enable Freescale DDR3 controller on ARM-based SoCs.
78 bool "Freescale DDR4 controller"
80 select SYS_FSL_DDRC_GEN4
82 Enable Freescale DDR4 controller.
84 config SYS_FSL_IFC_BANK_COUNT
85 int "Maximum banks of Integrated flash controller"
86 depends on ARCH_LS1021A