2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/cache.h>
12 #include <asm/system.h>
15 #include <fsl_esdhc.h>
21 #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
22 #define DCSR_RCPM2_CPMFSMCR0 0x400
23 #define DCSR_RCPM2_CPMFSMSR0 0x404
24 #define DCSR_RCPM2_CPMFSMCR1 0x414
25 #define DCSR_RCPM2_CPMFSMSR1 0x418
26 #define CPMFSMSR_FSM_STATE_MASK 0x7f
28 DECLARE_GLOBAL_DATA_PTR;
30 #ifndef CONFIG_SYS_DCACHE_OFF
33 * Bit[1] of the descriptor indicates the descriptor type,
34 * and bit[0] indicates whether the descriptor is valid.
36 #define PMD_TYPE_TABLE 0x3
37 #define PMD_TYPE_SECT 0x1
40 #define PMD_ATTRINDX(t) ((t) << 2)
43 #define PMD_SECT_AF (1 << 10)
45 #define BLOCK_SIZE_L1 (1UL << 30)
46 #define BLOCK_SIZE_L2 (1UL << 21)
49 #define TTBCR_EAE (1 << 31)
50 #define TTBCR_T0SZ(x) ((x) << 0)
51 #define TTBCR_T1SZ(x) ((x) << 16)
52 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
53 #define TTBCR_IRGN0_NC (0 << 8)
54 #define TTBCR_IRGN0_WBWA (1 << 8)
55 #define TTBCR_IRGN0_WT (2 << 8)
56 #define TTBCR_IRGN0_WBNWA (3 << 8)
57 #define TTBCR_IRGN0_MASK (3 << 8)
58 #define TTBCR_ORGN0_NC (0 << 10)
59 #define TTBCR_ORGN0_WBWA (1 << 10)
60 #define TTBCR_ORGN0_WT (2 << 10)
61 #define TTBCR_ORGN0_WBNWA (3 << 10)
62 #define TTBCR_ORGN0_MASK (3 << 10)
63 #define TTBCR_SHARED_NON (0 << 12)
64 #define TTBCR_SHARED_OUTER (2 << 12)
65 #define TTBCR_SHARED_INNER (3 << 12)
66 #define TTBCR_EPD0 (0 << 7)
67 #define TTBCR (TTBCR_SHARED_NON | \
74 * Memory region attributes for LPAE (defined in pgtable):
79 * UNCACHED 000 00000000
80 * BUFFERABLE 001 01000100
82 * WRITETHROUGH 010 10101010
83 * WRITEBACK 011 11101110
84 * DEV_CACHED 011 11101110
85 * DEV_SHARED 100 00000100
86 * DEV_NONSHARED 100 00000100
89 * WRITEALLOC 111 11111111
91 #define MT_MAIR0 0xeeaa4400
92 #define MT_MAIR1 0xff000004
93 #define MT_STRONLY_ORDER 0
94 #define MT_NORMAL_NC 1
95 #define MT_DEVICE_MEM 4
98 /* The phy_addr must be aligned to 4KB */
99 static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
101 u32 value = phy_addr | PMD_TYPE_TABLE;
103 page_table[2 * index] = value;
104 page_table[2 * index + 1] = 0;
107 /* The phy_addr must be aligned to 4KB */
108 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
113 value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
114 value |= PMD_ATTRINDX(memory_type);
115 page_table[2 * index] = value & 0xFFFFFFFF;
116 page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
120 * Start MMU after DDR is available, we create MMU table in DRAM.
121 * The base address of TTLB is gd->arch.tlb_addr. We use two
122 * levels of translation tables here to cover 40-bit address space.
124 * The TTLBs are located at PHY 2G~4G.
131 * |-------| <---- 0x24000000
132 * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
133 * |-------| <---- 0x300000000
135 * |-------| <---- 0x34000000
136 * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
137 * |-------| <---- 0x40000000
139 * |-------| <---- 0x80000000 DDR0 space start
141 *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
143 * ------- <---- 4GB DDR0 space end
145 static void mmu_setup(void)
147 u32 *level0_table = (u32 *)gd->arch.tlb_addr;
148 u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
153 /* Level 0 Table 2-3 are used to map DDR */
154 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
155 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
156 /* Level 0 Table 1 is used to map device */
157 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
158 /* Level 0 Table 0 is used to map device including PCIe MEM */
159 set_pgtable(level0_table, 0, (u32)level1_table);
161 /* Level 1 has 512 entries */
162 for (i = 0; i < 512; i++) {
163 /* Mapping for PCIe 1 */
164 if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
165 va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
166 CONFIG_SYS_PCIE_MMAP_SIZE))
167 set_pgsection(level1_table, i,
168 CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
170 /* Mapping for PCIe 2 */
171 else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
172 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
173 CONFIG_SYS_PCIE_MMAP_SIZE))
174 set_pgsection(level1_table, i,
175 CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
178 set_pgsection(level1_table, i,
181 va_start += BLOCK_SIZE_L2;
184 asm volatile("dsb sy;isb");
185 asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
186 : : "r" (TTBCR) : "memory");
187 asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
188 : : "r" ((u32)level0_table), "r" (0) : "memory");
189 asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
190 : : "r" (MT_MAIR0) : "memory");
191 asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
192 : : "r" (MT_MAIR1) : "memory");
194 /* Set the access control to all-supervisor */
195 asm volatile("mcr p15, 0, %0, c3, c0, 0"
204 * This function is called from lib/board.c. It recreates MMU
205 * table in main memory. MMU and i/d-cache are enabled here.
207 void enable_caches(void)
209 /* Invalidate all TLB */
210 mmu_page_table_flush(gd->arch.tlb_addr,
211 gd->arch.tlb_addr + gd->arch.tlb_size);
212 /* Set up and enable mmu */
215 /* Invalidate & Enable d-cache */
216 invalidate_dcache_all();
217 set_cr(get_cr() | CR_C);
219 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
221 #if defined(CONFIG_DISPLAY_CPUINFO)
222 int print_cpuinfo(void)
224 char buf1[32], buf2[32];
225 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
226 unsigned int svr, major, minor, ver, i;
228 svr = in_be32(&gur->svr);
229 major = SVR_MAJ(svr);
230 minor = SVR_MIN(svr);
232 puts("CPU: Freescale LayerScape ");
234 ver = SVR_SOC_VER(svr);
236 case SOC_VER_SLS1020:
253 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
256 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
258 puts("Clock Configuration:");
260 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
261 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
262 printf("DDR:%-4s MHz (%s MT/s data rate), ",
263 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
266 /* Display the RCW, so that no one gets confused as to what RCW
267 * we're actually using for this boot.
269 puts("Reset Configuration Word (RCW):");
270 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
271 u32 rcw = in_be32(&gur->rcwsr[i]);
274 printf("\n %08x:", i * 4);
275 printf(" %08x", rcw);
283 #ifdef CONFIG_FSL_ESDHC
284 int cpu_mmc_init(bd_t *bis)
286 return fsl_esdhc_mmc_init(bis);
290 int cpu_eth_init(bd_t *bis)
292 #ifdef CONFIG_TSEC_ENET
293 tsec_standard_init(bis);
299 int arch_cpu_init(void)
301 void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
303 (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
307 * The RCPM FSM state may not be reset after power-on.
310 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
311 CPMFSMSR_FSM_STATE_MASK;
313 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
314 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
317 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
318 CPMFSMSR_FSM_STATE_MASK;
320 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
321 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
325 * After wakeup from deep sleep, Clear EPU registers
326 * as early as possible to prevent from possible issue.
327 * It's also safe to clear at normal boot.
329 fsl_epu_clean(epu_base);
334 #ifdef CONFIG_ARMV7_NONSEC
335 /* Set the address at which the secondary core starts from.*/
336 void smp_set_core_boot_addr(unsigned long addr, int corenr)
338 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
340 out_be32(&gur->scratchrw[0], addr);
343 /* Release the secondary core from holdoff state and kick it */
344 void smp_kick_all_cpus(void)
346 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
348 out_be32(&gur->brrl, 0x2);
351 * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
352 * So add a delay to wait bootrom execute WFE.
360 void reset_cpu(ulong addr)
362 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
364 clrbits_be16(&wdog->wcr, WCR_SRS);
368 * Let the watchdog trigger