2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
10 #include <asm/arch/immap_ls102xa.h>
13 #include <fsl_esdhc.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #if defined(CONFIG_DISPLAY_CPUINFO)
18 int print_cpuinfo(void)
20 char buf1[32], buf2[32];
21 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
22 unsigned int svr, major, minor, ver, i;
24 svr = in_be32(&gur->svr);
28 puts("CPU: Freescale LayerScape ");
30 ver = SVR_SOC_VER(svr);
49 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
52 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
54 puts("Clock Configuration:");
56 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
57 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
58 printf("DDR:%-4s MHz (%s MT/s data rate), ",
59 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
62 /* Display the RCW, so that no one gets confused as to what RCW
63 * we're actually using for this boot.
65 puts("Reset Configuration Word (RCW):");
66 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
67 u32 rcw = in_be32(&gur->rcwsr[i]);
70 printf("\n %08x:", i * 4);
79 void enable_caches(void)
81 #ifndef CONFIG_SYS_ICACHE_OFF
84 #ifndef CONFIG_SYS_DCACHE_OFF
89 #ifdef CONFIG_FSL_ESDHC
90 int cpu_mmc_init(bd_t *bis)
92 return fsl_esdhc_mmc_init(bis);
96 int cpu_eth_init(bd_t *bis)
98 #ifdef CONFIG_TSEC_ENET
99 tsec_standard_init(bis);