2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
10 #include <asm/arch/immap_ls102xa.h>
13 #include <fsl_esdhc.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #if defined(CONFIG_DISPLAY_CPUINFO)
20 int print_cpuinfo(void)
22 char buf1[32], buf2[32];
23 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
24 unsigned int svr, major, minor, ver, i;
26 svr = in_be32(&gur->svr);
30 puts("CPU: Freescale LayerScape ");
32 ver = SVR_SOC_VER(svr);
51 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
54 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
56 puts("Clock Configuration:");
58 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
59 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
60 printf("DDR:%-4s MHz (%s MT/s data rate), ",
61 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
64 /* Display the RCW, so that no one gets confused as to what RCW
65 * we're actually using for this boot.
67 puts("Reset Configuration Word (RCW):");
68 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
69 u32 rcw = in_be32(&gur->rcwsr[i]);
72 printf("\n %08x:", i * 4);
81 void enable_caches(void)
83 #ifndef CONFIG_SYS_ICACHE_OFF
86 #ifndef CONFIG_SYS_DCACHE_OFF
91 #ifdef CONFIG_FSL_ESDHC
92 int cpu_mmc_init(bd_t *bis)
94 return fsl_esdhc_mmc_init(bis);
98 int cpu_eth_init(bd_t *bis)
100 #ifdef CONFIG_TSEC_ENET
101 tsec_standard_init(bis);
107 int arch_cpu_init(void)
109 void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
112 * After wakeup from deep sleep, Clear EPU registers
113 * as early as possible to prevent from possible issue.
114 * It's also safe to clear at normal boot.
116 fsl_epu_clean(epu_base);
121 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
122 /* Set the address at which the secondary core starts from.*/
123 void smp_set_core_boot_addr(unsigned long addr, int corenr)
125 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
127 out_be32(&gur->scratchrw[0], addr);
130 /* Release the secondary core from holdoff state and kick it */
131 void smp_kick_all_cpus(void)
133 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
135 out_be32(&gur->brrl, 0x2);