git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/ls102xa/fdt.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <libfdt.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #include <asm/arch/clock.h>
  13 #include <linux/ctype.h>
  14 #ifdef CONFIG_FSL_ESDHC
  15 #include <fsl_esdhc.h>
  16 #endif
  17 #include <tsec.h>
  18 #include <asm/arch/immap_ls102xa.h>
  19 #include <fsl_sec.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 void ft_fixup_enet_phy_connect_type(void *fdt)
  24 {
  25         struct eth_device *dev;
  26         struct tsec_private *priv;
  27         const char *enet_path, *phy_path;
  28         char enet[16];
  29         char phy[16];
  30         int phy_node;
  31         int i = 0;
  32         uint32_t ph;
  33         char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
  34
  35         for (; i < ARRAY_SIZE(name); i++) {
  36                 dev = eth_get_dev_by_name(name[i]);
  37                 if (dev) {
  38                         sprintf(enet, "ethernet%d", i);
  39                         sprintf(phy, "enet%d_rgmii_phy", i);
  40                 } else {
  41                         continue;
  42                 }
  43
  44                 priv = dev->priv;
  45                 if (priv->flags & TSEC_SGMII)
  46                         continue;
  47
  48                 enet_path = fdt_get_alias(fdt, enet);
  49                 if (!enet_path)
  50                         continue;
  51
  52                 phy_path = fdt_get_alias(fdt, phy);
  53                 if (!phy_path)
  54                         continue;
  55
  56                 phy_node = fdt_path_offset(fdt, phy_path);
  57                 if (phy_node < 0)
  58                         continue;
  59
  60                 ph = fdt_create_phandle(fdt, phy_node);
  61                 if (ph)
  62                         do_fixup_by_path_u32(fdt, enet_path,
  63                                              "phy-handle", ph, 1);
  64
  65                 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  66                                  phy_string_for_interface(
  67                                  PHY_INTERFACE_MODE_RGMII_ID),
  68                                  sizeof(phy_string_for_interface(
  69                                  PHY_INTERFACE_MODE_RGMII_ID)),
  70                                  1);
  71         }
  72 }
  73
  74 void ft_cpu_setup(void *blob, bd_t *bd)
  75 {
  76         int off;
  77         int val;
  78         const char *sysclk_path;
  79         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  80         unsigned int svr;
  81         svr = in_be32(&gur->svr);
  82
  83         unsigned long busclk = get_bus_freq(0);
  84
  85         /* delete crypto node if not on an E-processor */
  86         if (!IS_E_PROCESSOR(svr))
  87                 fdt_fixup_crypto_node(blob, 0);
  88 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  89         else {
  90                 ccsr_sec_t __iomem *sec;
  91
  92                 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  93                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  94         }
  95 #endif
  96
  97         fdt_fixup_ethernet(blob);
  98
  99         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 100         while (off != -FDT_ERR_NOTFOUND) {
 101                 val = gd->cpu_clk;
 102                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 103                 off = fdt_node_offset_by_prop_value(blob, off,
 104                                                     "device_type", "cpu", 4);
 105         }
 106
 107         do_fixup_by_prop_u32(blob, "device_type", "soc",
 108                              4, "bus-frequency", busclk, 1);
 109
 110         ft_fixup_enet_phy_connect_type(blob);
 111
 112 #ifdef CONFIG_SYS_NS16550
 113         do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
 114                                "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 115 #endif
 116
 117         sysclk_path = fdt_get_alias(blob, "sysclk");
 118         if (sysclk_path)
 119                 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
 120                                      CONFIG_SYS_CLK_FREQ, 1);
 121         do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
 122                                "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 123
 124 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 125 #define UBOOT_HEAD_LEN  0x1000
 126         /*
 127          * Reserved memory in SD boot deep sleep case.
 128          * Second stage uboot binary and malloc space should be reserved.
 129          * If the memory they occupied has not been reserved, then this
 130          * space would be used by kernel and overwritten in uboot when
 131          * deep sleep resume, which cause deep sleep failed.
 132          * Since second uboot binary has a head, that space need to be
 133          * reserved either(assuming its size is less than 0x1000).
 134          */
 135         off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
 136                         CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
 137                         UBOOT_HEAD_LEN);
 138         if (off < 0)
 139                 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
 140                        fdt_strerror(off));
 141 #endif
 142
 143 #if defined(CONFIG_FSL_ESDHC)
 144         fdt_fixup_esdhc(blob, bd);
 145 #endif
 146
 147         /*
 148          * platform bus clock = system bus clock/2
 149          * Here busclk = system bus clock
 150          * We are using the platform bus clock as 1588 Timer reference
 151          * clock source select
 152          */
 153         do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
 154                                "timer-frequency", busclk / 2, 1);
 155
 156         /*
 157          * clock-freq should change to clock-frequency and
 158          * flexcan-v1.0 should change to p1010-flexcan respectively
 159          * in the future.
 160          */
 161         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 162                                "clock_freq", busclk / 2, 1);
 163
 164         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 165                                "clock-frequency", busclk / 2, 1);
 166
 167         do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
 168                                "clock-frequency", busclk / 2, 1);
 169
 170 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 171         off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 172                                             CONFIG_SYS_IFC_ADDR);
 173         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 174 #else
 175         off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 176                                             QSPI0_BASE_ADDR);
 177         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 178         off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 179                                             DSPI1_BASE_ADDR);
 180         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 181 #endif
 182 }