2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/processor.h>
12 #include <asm/arch/clock.h>
13 #include <linux/ctype.h>
14 #ifdef CONFIG_FSL_ESDHC
15 #include <fsl_esdhc.h>
18 #include <asm/arch/immap_ls102xa.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 void ft_fixup_enet_phy_connect_type(void *fdt)
25 struct eth_device *dev;
26 struct tsec_private *priv;
27 const char *enet_path, *phy_path;
33 char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
35 for (; i < ARRAY_SIZE(name); i++) {
36 dev = eth_get_dev_by_name(name[i]);
38 sprintf(enet, "ethernet%d", i);
39 sprintf(phy, "enet%d_rgmii_phy", i);
45 if (priv->flags & TSEC_SGMII)
48 enet_path = fdt_get_alias(fdt, enet);
52 phy_path = fdt_get_alias(fdt, phy);
56 phy_node = fdt_path_offset(fdt, phy_path);
60 ph = fdt_create_phandle(fdt, phy_node);
62 do_fixup_by_path_u32(fdt, enet_path,
65 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
66 phy_string_for_interface(
67 PHY_INTERFACE_MODE_RGMII_ID),
68 sizeof(phy_string_for_interface(
69 PHY_INTERFACE_MODE_RGMII_ID)),
74 void ft_cpu_setup(void *blob, bd_t *bd)
78 const char *sysclk_path;
79 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
81 svr = in_be32(&gur->svr);
83 unsigned long busclk = get_bus_freq(0);
85 /* delete crypto node if not on an E-processor */
86 if (!IS_E_PROCESSOR(svr))
87 fdt_fixup_crypto_node(blob, 0);
88 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
90 ccsr_sec_t __iomem *sec;
92 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
93 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
97 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
98 while (off != -FDT_ERR_NOTFOUND) {
100 fdt_setprop(blob, off, "clock-frequency", &val, 4);
101 off = fdt_node_offset_by_prop_value(blob, off,
102 "device_type", "cpu", 4);
105 do_fixup_by_prop_u32(blob, "device_type", "soc",
106 4, "bus-frequency", busclk, 1);
108 ft_fixup_enet_phy_connect_type(blob);
110 #ifdef CONFIG_SYS_NS16550
111 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
112 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
115 sysclk_path = fdt_get_alias(blob, "sysclk");
117 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
118 CONFIG_SYS_CLK_FREQ, 1);
119 do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
120 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
122 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
123 #define UBOOT_HEAD_LEN 0x1000
125 * Reserved memory in SD boot deep sleep case.
126 * Second stage uboot binary and malloc space should be reserved.
127 * If the memory they occupied has not been reserved, then this
128 * space would be used by kernel and overwritten in uboot when
129 * deep sleep resume, which cause deep sleep failed.
130 * Since second uboot binary has a head, that space need to be
131 * reserved either(assuming its size is less than 0x1000).
133 off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
134 CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
137 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
141 #if defined(CONFIG_FSL_ESDHC)
142 fdt_fixup_esdhc(blob, bd);
146 * platform bus clock = system bus clock/2
147 * Here busclk = system bus clock
148 * We are using the platform bus clock as 1588 Timer reference
149 * clock source select
151 do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
152 "timer-frequency", busclk / 2, 1);
155 * clock-freq should change to clock-frequency and
156 * flexcan-v1.0 should change to p1010-flexcan respectively
159 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
160 "clock_freq", busclk / 2, 1);
162 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
163 "clock-frequency", busclk / 2, 1);
165 do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
166 "clock-frequency", busclk / 2, 1);
168 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
169 off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
170 CONFIG_SYS_IFC_ADDR);
171 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
173 off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
175 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
176 off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
178 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);