2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/processor.h>
12 #include <asm/arch/clock.h>
13 #include <linux/ctype.h>
14 #ifdef CONFIG_FSL_ESDHC
15 #include <fsl_esdhc.h>
18 #include <asm/arch/immap_ls102xa.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 void ft_fixup_enet_phy_connect_type(void *fdt)
25 struct eth_device *dev;
26 struct tsec_private *priv;
27 const char *enet_path, *phy_path;
34 while ((dev = eth_get_dev_by_index(i++)) != NULL) {
35 if (strstr(dev->name, "eTSEC1")) {
36 strcpy(enet, "ethernet0");
37 strcpy(phy, "enet0_rgmii_phy");
38 } else if (strstr(dev->name, "eTSEC2")) {
39 strcpy(enet, "ethernet1");
40 strcpy(phy, "enet1_rgmii_phy");
41 } else if (strstr(dev->name, "eTSEC3")) {
42 strcpy(enet, "ethernet2");
43 strcpy(phy, "enet2_rgmii_phy");
49 if (priv->flags & TSEC_SGMII)
52 enet_path = fdt_get_alias(fdt, enet);
56 phy_path = fdt_get_alias(fdt, phy);
60 phy_node = fdt_path_offset(fdt, phy_path);
64 ph = fdt_create_phandle(fdt, phy_node);
66 do_fixup_by_path_u32(fdt, enet_path,
69 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
70 phy_string_for_interface(
71 PHY_INTERFACE_MODE_RGMII_ID),
72 sizeof(phy_string_for_interface(
73 PHY_INTERFACE_MODE_RGMII_ID)),
78 void ft_cpu_setup(void *blob, bd_t *bd)
82 const char *sysclk_path;
83 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
85 svr = in_be32(&gur->svr);
87 unsigned long busclk = get_bus_freq(0);
89 /* delete crypto node if not on an E-processor */
90 if (!IS_E_PROCESSOR(svr))
91 fdt_fixup_crypto_node(blob, 0);
92 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
94 ccsr_sec_t __iomem *sec;
96 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
97 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
101 fdt_fixup_ethernet(blob);
103 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
104 while (off != -FDT_ERR_NOTFOUND) {
106 fdt_setprop(blob, off, "clock-frequency", &val, 4);
107 off = fdt_node_offset_by_prop_value(blob, off,
108 "device_type", "cpu", 4);
111 do_fixup_by_prop_u32(blob, "device_type", "soc",
112 4, "bus-frequency", busclk, 1);
114 ft_fixup_enet_phy_connect_type(blob);
116 #ifdef CONFIG_SYS_NS16550
117 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
118 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
121 sysclk_path = fdt_get_alias(blob, "sysclk");
123 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
124 CONFIG_SYS_CLK_FREQ, 1);
125 do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
126 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
128 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
129 #define UBOOT_HEAD_LEN 0x1000
131 * Reserved memory in SD boot deep sleep case.
132 * Second stage uboot binary and malloc space should be reserved.
133 * If the memory they occupied has not been reserved, then this
134 * space would be used by kernel and overwritten in uboot when
135 * deep sleep resume, which cause deep sleep failed.
136 * Since second uboot binary has a head, that space need to be
137 * reserved either(assuming its size is less than 0x1000).
139 off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
140 CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
143 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
147 #if defined(CONFIG_FSL_ESDHC)
148 fdt_fixup_esdhc(blob, bd);
152 * platform bus clock = system bus clock/2
153 * Here busclk = system bus clock
154 * We are using the platform bus clock as 1588 Timer reference
155 * clock source select
157 do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
158 "timer-frequency", busclk / 2, 1);
161 * clock-freq should change to clock-frequency and
162 * flexcan-v1.0 should change to p1010-flexcan respectively
165 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
166 "clock_freq", busclk / 2, 1);
168 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
169 "clock-frequency", busclk / 2, 1);
171 do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
172 "clock-frequency", busclk / 2, 1);
174 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
175 off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
176 CONFIG_SYS_IFC_ADDR);
177 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
179 off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
181 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
182 off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
184 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);