2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/fsl_serdes.h>
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/errno.h>
12 #include "fsl_ls1_serdes.h"
14 #ifdef CONFIG_SYS_FSL_SRDS_1
15 static u64 serdes1_prtcl_map;
17 #ifdef CONFIG_SYS_FSL_SRDS_2
18 static u64 serdes2_prtcl_map;
21 int is_serdes_configured(enum srds_prtcl device)
25 #ifdef CONFIG_SYS_FSL_SRDS_1
26 ret |= (1ULL << device) & serdes1_prtcl_map;
28 #ifdef CONFIG_SYS_FSL_SRDS_2
29 ret |= (1ULL << device) & serdes2_prtcl_map;
35 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
37 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
38 u32 cfg = in_be32(&gur->rcwsr[4]);
42 #ifdef CONFIG_SYS_FSL_SRDS_1
44 cfg &= RCWSR4_SRDS1_PRTCL_MASK;
45 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
48 #ifdef CONFIG_SYS_FSL_SRDS_2
50 cfg &= RCWSR4_SRDS2_PRTCL_MASK;
51 cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
55 printf("invalid SerDes%d\n", sd);
58 /* Is serdes enabled at all? */
59 if (unlikely(cfg == 0))
62 for (i = 0; i < SRDS_MAX_LANES; i++) {
63 if (serdes_get_prtcl(sd, cfg, i) == device)
70 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
72 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
73 u64 serdes_prtcl_map = 0;
77 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
78 cfg >>= sd_prctl_shift;
79 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
81 if (!is_serdes_prtcl_valid(sd, cfg))
82 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
84 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
85 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
87 serdes_prtcl_map |= (1ULL << lane_prtcl);
90 return serdes_prtcl_map;
93 void fsl_serdes_init(void)
95 #ifdef CONFIG_SYS_FSL_SRDS_1
96 serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
97 CONFIG_SYS_FSL_SERDES_ADDR,
98 RCWSR4_SRDS1_PRTCL_MASK,
99 RCWSR4_SRDS1_PRTCL_SHIFT);
101 #ifdef CONFIG_SYS_FSL_SRDS_2
102 serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
103 CONFIG_SYS_FSL_SERDES_ADDR +
105 RCWSR4_SRDS2_PRTCL_MASK,
106 RCWSR4_SRDS2_PRTCL_SHIFT);
110 const char *serdes_clock_to_string(u32 clock)
113 case SRDS_PLLCR0_RFCK_SEL_100:
115 case SRDS_PLLCR0_RFCK_SEL_125: