2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/linkage.h>
11 #include <asm/armv7.h>
12 #include <asm/arch-armv7/generictimer.h>
15 #define SCFG_CORE0_SFT_RST 0x130
16 #define SCFG_CORESRENCR 0x204
18 #define DCFG_CCSR_BRR 0x0E4
19 #define DCFG_CCSR_SCRATCHRW1 0x200
21 .pushsection ._secure.text, "ax"
25 #define ONE_MS (GENERIC_TIMER_CLK / 1000)
26 #define RESET_WAIT (30 * ONE_MS)
34 @ Clear and Get the correct CPU number
39 bl psci_get_cpu_stack_top
43 @ Get DCFG base address
44 movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
45 movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
47 @ Detect target CPU state
48 ldr r2, [r4, #DCFG_CCSR_BRR]
55 @ Get SCFG base address
56 movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
57 movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
59 @ Enable CORE Soft Reset
63 str r5, [r0, #SCFG_CORESRENCR]
65 @ Get CPUx offset register
70 @ Do reset on target CPU
74 str r5, [r2, #SCFG_CORE0_SFT_RST]
77 timer_wait r2, RESET_WAIT
79 @ Disable CORE soft reset
81 str r5, [r0, #SCFG_CORESRENCR]
84 @ Release on target CPU
85 ldr r2, [r4, #DCFG_CCSR_BRR]
87 lsl r6, r6, r1 @ 32 bytes per CPU
91 str r2, [r4, #DCFG_CCSR_BRR]
93 @ Set secondary boot entry
94 ldr r6, =psci_cpu_entry
96 str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
102 mov r0, #ARM_PSCI_RET_SUCCESS
109 bl psci_cpu_off_common
114 .globl psci_arch_init
119 bl psci_get_cpu_stack_top