2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/linkage.h>
11 #include <asm/armv7.h>
12 #include <asm/arch-armv7/generictimer.h>
15 #define RCPM_TWAITSR 0x04C
17 #define SCFG_CORE0_SFT_RST 0x130
18 #define SCFG_CORESRENCR 0x204
20 #define DCFG_CCSR_RSTCR 0x0B0
21 #define DCFG_CCSR_RSTCR_RESET_REQ 0x2
22 #define DCFG_CCSR_BRR 0x0E4
23 #define DCFG_CCSR_SCRATCHRW1 0x200
25 #define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
26 #define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
27 #define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
28 #define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
29 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
30 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
31 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
32 #define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
34 .pushsection ._secure.text, "ax"
40 #define ONE_MS (COUNTER_FREQUENCY / 1000)
41 #define RESET_WAIT (30 * ONE_MS)
50 _ls102x_psci_supported_table:
51 .word ARM_PSCI_0_2_FN_PSCI_VERSION
52 .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
53 .word ARM_PSCI_0_2_FN_CPU_SUSPEND
54 .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
55 .word ARM_PSCI_0_2_FN_CPU_OFF
56 .word PSCI_FN_CPU_OFF_FEATURE_MASK
57 .word ARM_PSCI_0_2_FN_CPU_ON
58 .word PSCI_FN_CPU_ON_FEATURE_MASK
59 .word ARM_PSCI_0_2_FN_AFFINITY_INFO
60 .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
61 .word ARM_PSCI_0_2_FN_SYSTEM_OFF
62 .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
63 .word ARM_PSCI_0_2_FN_SYSTEM_RESET
64 .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
65 .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
66 .word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
72 adr r2, _ls102x_psci_supported_table
84 @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
85 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
86 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
87 @ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
88 LENTRY(psci_check_target_cpu_id)
89 @ Get the real CPU number
91 mov r0, #ARM_PSCI_RET_INVAL
93 @ Bit[31:24], bits must be zero.
97 @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
101 @ Affinity level 1 - Processors: should be in 0xf00 format.
106 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
110 mov r0, #ARM_PSCI_RET_SUCCESS
112 ENDPROC(psci_check_target_cpu_id)
118 push {r4, r5, r6, lr}
120 @ Clear and Get the correct CPU number
122 bl psci_check_target_cpu_id
123 cmp r0, #ARM_PSCI_RET_INVAL
128 bl psci_save_target_pc
131 @ Get DCFG base address
132 movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
133 movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
135 @ Detect target CPU state
136 ldr r2, [r4, #DCFG_CCSR_BRR]
143 @ Get SCFG base address
144 movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
145 movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
147 @ Enable CORE Soft Reset
151 str r5, [r0, #SCFG_CORESRENCR]
153 @ Get CPUx offset register
158 @ Do reset on target CPU
162 str r5, [r2, #SCFG_CORE0_SFT_RST]
165 timer_wait r2, RESET_WAIT
167 @ Disable CORE soft reset
169 str r5, [r0, #SCFG_CORESRENCR]
172 @ Release on target CPU
173 ldr r2, [r4, #DCFG_CCSR_BRR]
175 lsl r6, r6, r1 @ 32 bytes per CPU
179 str r2, [r4, #DCFG_CCSR_BRR]
181 @ Set secondary boot entry
182 ldr r6, =psci_cpu_entry
184 str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
190 mov r0, #ARM_PSCI_RET_SUCCESS
198 bl psci_cpu_off_common
203 .globl psci_affinity_info
207 mov r0, #ARM_PSCI_RET_INVAL
209 @ Verify Affinity level
211 bne out_affinity_info
213 bl psci_check_target_cpu_id
214 cmp r0, #ARM_PSCI_RET_INVAL
215 beq out_affinity_info
218 @ Get RCPM base address
219 movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
220 movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
222 mov r0, #PSCI_AFFINITY_LEVEL_ON
224 @ Detect target CPU state
225 ldr r2, [r4, #RCPM_TWAITSR]
229 beq out_affinity_info
231 mov r0, #PSCI_AFFINITY_LEVEL_OFF
236 .globl psci_system_reset
238 @ Get DCFG base address
239 movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
240 movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
242 mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
244 str r2, [r1, #DCFG_CCSR_RSTCR]
249 .globl psci_system_suspend
253 bl ls1_system_suspend