git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/ls102xa/soc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ls102xa_soc.h>
  12 #include <asm/arch/ls102xa_stream_id.h>
  13 #include <fsl_csu.h>
  14
  15 struct liodn_id_table sec_liodn_tbl[] = {
  16         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  17         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  18         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  19         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  20         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  21         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  22         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  23         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  24         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  25         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  26         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  27         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  28         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  29         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  30         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  31         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  32 };
  33
  34 struct smmu_stream_id dev_stream_id[] = {
  35         { 0x100, 0x01, "ETSEC MAC1" },
  36         { 0x104, 0x02, "ETSEC MAC2" },
  37         { 0x108, 0x03, "ETSEC MAC3" },
  38         { 0x10c, 0x04, "PEX1" },
  39         { 0x110, 0x05, "PEX2" },
  40         { 0x114, 0x06, "qDMA" },
  41         { 0x118, 0x07, "SATA" },
  42         { 0x11c, 0x08, "USB3" },
  43         { 0x120, 0x09, "QE" },
  44         { 0x124, 0x0a, "eSDHC" },
  45         { 0x128, 0x0b, "eMA" },
  46         { 0x14c, 0x0c, "2D-ACE" },
  47         { 0x150, 0x0d, "USB2" },
  48         { 0x18c, 0x0e, "DEBUG" },
  49 };
  50
  51 unsigned int get_soc_major_rev(void)
  52 {
  53         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  54         unsigned int svr, major;
  55
  56         svr = in_be32(&gur->svr);
  57         major = SVR_MAJ(svr);
  58
  59         return major;
  60 }
  61
  62 int arch_soc_init(void)
  63 {
  64         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  65         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  66         unsigned int major;
  67
  68 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  69         enable_layerscape_ns_access();
  70 #endif
  71
  72 #ifdef CONFIG_FSL_QSPI
  73         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  74 #endif
  75
  76 #ifdef CONFIG_FSL_DCU_FB
  77         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
  78 #endif
  79
  80         /* Configure Little endian for SAI, ASRC and SPDIF */
  81         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
  82
  83         /*
  84          * Enable snoop requests and DVM message requests for
  85          * All the slave insterfaces.
  86          */
  87         out_le32(&cci->slave[0].snoop_ctrl,
  88                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  89         out_le32(&cci->slave[1].snoop_ctrl,
  90                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  91         out_le32(&cci->slave[2].snoop_ctrl,
  92                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  93         out_le32(&cci->slave[4].snoop_ctrl,
  94                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  95
  96         major = get_soc_major_rev();
  97         if (major == SOC_MAJOR_VER_1_0) {
  98                 /*
  99                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 100                  * Register All transactions are treated as non-shareable
 101                  */
 102                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 103                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 104
 105                 /* Workaround for the issue that DDR could not respond to
 106                  * barrier transaction which is generated by executing DSB/ISB
 107                  * instruction. Set CCI-400 control override register to
 108                  * terminate the barrier transaction. After DDR is initialized,
 109                  * allow barrier transaction to DDR again */
 110                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 111         }
 112
 113         /* Enable all the snoop signal for various masters */
 114         out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 115                                 SCFG_SNPCNFGCR_DCU_RD_WR |
 116                                 SCFG_SNPCNFGCR_SATA_RD_WR |
 117                                 SCFG_SNPCNFGCR_USB3_RD_WR |
 118                                 SCFG_SNPCNFGCR_DBG_RD_WR |
 119                                 SCFG_SNPCNFGCR_EDMA_SNP);
 120
 121         /*
 122          * Memory controller require a register write before being enabled.
 123          * Affects: DDR
 124          * Register: EDDRTQCFG
 125          * Description: Memory controller performance is not optimal with
 126          *              default internal target queue register values.
 127          * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 128          */
 129         out_be32(&scfg->eddrtqcfg, 0x63b20042);
 130
 131         return 0;
 132 }
 133
 134 int ls102xa_smmu_stream_id_init(void)
 135 {
 136         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 137                                       ARRAY_SIZE(sec_liodn_tbl));
 138
 139         ls102xa_config_smmu_stream_id(dev_stream_id,
 140                                       ARRAY_SIZE(dev_stream_id));
 141
 142         return 0;
 143 }