3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
43 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
44 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
45 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
46 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
48 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
52 #define AHB_CLK_ROOT 133333333
53 #define SZ_DEC_1M 1000000
54 #define PLL_PD_MAX 16 /* Actual pd+1 */
55 #define PLL_MFI_MAX 15
63 #define MX5_CBCMR 0x00015154
64 #define MX5_CBCDR 0x02888945
66 struct fixed_pll_mfd {
71 const struct fixed_pll_mfd fixed_mfd[] = {
72 {CONFIG_SYS_MX5_HCLK, 24 * 16},
82 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
83 #define PLL_FREQ_MIN(ref_clk) \
84 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
85 #define MAX_DDR_CLK 420000000
86 #define NFC_CLK_MAX 34000000
88 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
90 void set_usboh3_clk(void)
94 reg = readl(&mxc_ccm->cscmr1) &
95 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
96 reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
97 writel(reg, &mxc_ccm->cscmr1);
99 reg = readl(&mxc_ccm->cscdr1);
100 reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
101 reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
102 reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
103 reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
105 writel(reg, &mxc_ccm->cscdr1);
108 void enable_usboh3_clk(unsigned char enable)
112 reg = readl(&mxc_ccm->CCGR2);
114 reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
116 reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
117 writel(reg, &mxc_ccm->CCGR2);
120 #ifdef CONFIG_I2C_MXC
121 /* i2c_num can be from 0 - 2 */
122 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
129 mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
130 reg = __raw_readl(&mxc_ccm->CCGR1);
135 __raw_writel(reg, &mxc_ccm->CCGR1);
140 void set_usb_phy1_clk(void)
144 reg = readl(&mxc_ccm->cscmr1);
145 reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
146 writel(reg, &mxc_ccm->cscmr1);
149 void enable_usb_phy1_clk(unsigned char enable)
153 reg = readl(&mxc_ccm->CCGR4);
155 reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
157 reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
158 writel(reg, &mxc_ccm->CCGR4);
161 void set_usb_phy2_clk(void)
165 reg = readl(&mxc_ccm->cscmr1);
166 reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
167 writel(reg, &mxc_ccm->cscmr1);
170 void enable_usb_phy2_clk(unsigned char enable)
174 reg = readl(&mxc_ccm->CCGR4);
176 reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
178 reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
179 writel(reg, &mxc_ccm->CCGR4);
183 * Calculate the frequency of PLLn.
185 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
187 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
188 uint64_t refclk, temp;
191 ctrl = readl(&pll->ctrl);
193 if (ctrl & MXC_DPLLC_CTL_HFSM) {
194 mfn = __raw_readl(&pll->hfs_mfn);
195 mfd = __raw_readl(&pll->hfs_mfd);
196 op = __raw_readl(&pll->hfs_op);
198 mfn = __raw_readl(&pll->mfn);
199 mfd = __raw_readl(&pll->mfd);
200 op = __raw_readl(&pll->op);
203 mfd &= MXC_DPLLC_MFD_MFD_MASK;
204 mfn &= MXC_DPLLC_MFN_MFN_MASK;
205 pdf = op & MXC_DPLLC_OP_PDF_MASK;
206 mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
213 if (mfn >= 0x04000000) {
220 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
223 do_div(refclk, pdf + 1);
224 temp = refclk * mfn_abs;
225 do_div(temp, mfd + 1);
239 u32 get_mcu_main_clk(void)
243 reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
244 MXC_CCM_CACRR_ARM_PODF_OFFSET;
245 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
246 return freq / (reg + 1);
250 * Get the rate of peripheral's root clock.
252 u32 get_periph_clk(void)
256 reg = __raw_readl(&mxc_ccm->cbcdr);
257 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
258 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
259 reg = __raw_readl(&mxc_ccm->cbcmr);
260 switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
261 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
263 return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
265 return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
273 * Get the rate of ipg clock.
275 static u32 get_ipg_clk(void)
277 uint32_t freq, reg, div;
279 freq = get_ahb_clk();
281 reg = __raw_readl(&mxc_ccm->cbcdr);
282 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
283 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
289 * Get the rate of ipg_per clock.
291 static u32 get_ipg_per_clk(void)
293 u32 pred1, pred2, podf;
295 if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
296 return get_ipg_clk();
297 /* Fixme: not handle what about lpm*/
298 podf = __raw_readl(&mxc_ccm->cbcdr);
299 pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
300 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
301 pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
302 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
303 podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
304 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
306 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
310 * Get the rate of uart clk.
312 static u32 get_uart_clk(void)
314 unsigned int freq, reg, pred, podf;
316 reg = __raw_readl(&mxc_ccm->cscmr1);
317 switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
318 MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
320 freq = decode_pll(mxc_plls[PLL1_CLOCK],
321 CONFIG_SYS_MX5_HCLK);
324 freq = decode_pll(mxc_plls[PLL2_CLOCK],
325 CONFIG_SYS_MX5_HCLK);
328 freq = decode_pll(mxc_plls[PLL3_CLOCK],
329 CONFIG_SYS_MX5_HCLK);
335 reg = __raw_readl(&mxc_ccm->cscdr1);
337 pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
338 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
340 podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
341 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
342 freq /= (pred + 1) * (podf + 1);
348 * This function returns the low power audio clock.
350 static u32 get_lp_apm(void)
353 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
355 if (((ccsr >> 9) & 1) == 0)
356 ret_val = CONFIG_SYS_MX5_HCLK;
358 ret_val = ((32768 * 1024));
364 * get cspi clock rate.
366 static u32 imx_get_cspiclk(void)
368 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
369 u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
370 u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
372 pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
373 >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
374 pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
375 >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
376 clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
377 >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
381 ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
382 CONFIG_SYS_MX5_HCLK) /
383 ((pre_pdf + 1) * (pdf + 1));
386 ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
387 CONFIG_SYS_MX5_HCLK) /
388 ((pre_pdf + 1) * (pdf + 1));
391 ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
392 CONFIG_SYS_MX5_HCLK) /
393 ((pre_pdf + 1) * (pdf + 1));
396 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
403 static u32 get_axi_a_clk(void)
405 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
406 u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
407 >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
409 return get_periph_clk() / (pdf + 1);
412 static u32 get_axi_b_clk(void)
414 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
415 u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
416 >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
418 return get_periph_clk() / (pdf + 1);
421 static u32 get_emi_slow_clk(void)
423 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
424 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
425 u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
426 >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
429 return get_ahb_clk() / (pdf + 1);
431 return get_periph_clk() / (pdf + 1);
434 static u32 get_ddr_clk(void)
437 u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
438 u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
439 >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
441 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
442 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
443 u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
444 MXC_CCM_CBCDR_DDR_PODF_OFFSET;
446 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
447 ret_val /= ddr_clk_podf + 1;
452 switch (ddr_clk_sel) {
454 ret_val = get_axi_a_clk();
457 ret_val = get_axi_b_clk();
460 ret_val = get_emi_slow_clk();
463 ret_val = get_ahb_clk();
473 * The API of get mxc clocks.
475 unsigned int mxc_get_clock(enum mxc_clock clk)
479 return get_mcu_main_clk();
481 return get_ahb_clk();
483 return get_ipg_clk();
485 return get_ipg_per_clk();
487 return get_uart_clk();
489 return imx_get_cspiclk();
491 return decode_pll(mxc_plls[PLL1_CLOCK],
492 CONFIG_SYS_MX5_HCLK);
494 return get_ahb_clk();
496 return get_ddr_clk();
503 u32 imx_get_uartclk(void)
505 return get_uart_clk();
509 u32 imx_get_fecclk(void)
511 return mxc_get_clock(MXC_IPG_CLK);
514 static int gcd(int m, int n)
529 * This is to calculate various parameters based on reference clock and
530 * targeted clock based on the equation:
531 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
532 * This calculation is based on a fixed MFD value for simplicity.
534 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
536 u64 pd, mfi = 1, mfn, mfd, t1;
537 u32 n_target = target;
541 * Make sure targeted freq is in the valid range.
542 * Otherwise the following calculation might be wrong!!!
544 if (n_target < PLL_FREQ_MIN(ref) ||
545 n_target > PLL_FREQ_MAX(ref)) {
546 printf("Targeted peripheral clock should be"
547 "within [%d - %d]\n",
548 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
549 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
553 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
554 if (fixed_mfd[i].ref_clk_hz == ref) {
555 mfd = fixed_mfd[i].mfd;
560 if (i == ARRAY_SIZE(fixed_mfd))
563 /* Use n_target and n_ref to avoid overflow */
564 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
566 do_div(t1, (4 * n_ref));
568 if (mfi > PLL_MFI_MAX)
575 * Now got pd and mfi already
577 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
585 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
586 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
600 #define calc_div(tgt_clk, src_clk, limit) ({ \
602 if (((src_clk) % (tgt_clk)) <= 100) \
603 v = (src_clk) / (tgt_clk); \
605 v = ((src_clk) / (tgt_clk)) + 1;\
611 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
613 __raw_writel(0x1232, &pll->ctrl); \
614 __raw_writel(0x2, &pll->config); \
615 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
617 __raw_writel(fn, &(pll->mfn)); \
618 __raw_writel((fd) - 1, &pll->mfd); \
619 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
621 __raw_writel(fn, &pll->hfs_mfn); \
622 __raw_writel((fd) - 1, &pll->hfs_mfd); \
623 __raw_writel(0x1232, &pll->ctrl); \
624 while (!__raw_readl(&pll->ctrl) & 0x1) \
628 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
630 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
631 struct mxc_pll_reg *pll = mxc_plls[index];
635 /* Switch ARM to PLL2 clock */
636 __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
637 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
638 pll_param->mfi, pll_param->mfn,
641 __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
644 /* Switch to pll2 bypass clock */
645 __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
646 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
647 pll_param->mfi, pll_param->mfn,
650 __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
653 /* Switch to pll3 bypass clock */
654 __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
655 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
656 pll_param->mfi, pll_param->mfn,
659 __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
662 /* Switch to pll4 bypass clock */
663 __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
664 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
665 pll_param->mfi, pll_param->mfn,
668 __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
677 /* Config CPU clock */
678 static int config_core_clk(u32 ref, u32 freq)
681 struct pll_param pll_param;
683 memset(&pll_param, 0, sizeof(struct pll_param));
685 /* The case that periph uses PLL1 is not considered here */
686 ret = calc_pll_params(ref, freq, &pll_param);
688 printf("Error:Can't find pll parameters: %d\n", ret);
692 return config_pll_clk(PLL1_CLOCK, &pll_param);
695 static int config_nfc_clk(u32 nfc_clk)
698 u32 parent_rate = get_emi_slow_clk();
699 u32 div = parent_rate / nfc_clk;
705 if (parent_rate / div > NFC_CLK_MAX)
707 reg = __raw_readl(&mxc_ccm->cbcdr);
708 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
709 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
710 __raw_writel(reg, &mxc_ccm->cbcdr);
711 while (__raw_readl(&mxc_ccm->cdhipr) != 0)
716 /* Config main_bus_clock for periphs */
717 static int config_periph_clk(u32 ref, u32 freq)
720 struct pll_param pll_param;
722 memset(&pll_param, 0, sizeof(struct pll_param));
724 if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
725 ret = calc_pll_params(ref, freq, &pll_param);
727 printf("Error:Can't find pll parameters: %d\n",
731 switch ((__raw_readl(&mxc_ccm->cbcmr) & \
732 MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
733 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
735 return config_pll_clk(PLL1_CLOCK, &pll_param);
738 return config_pll_clk(PLL3_CLOCK, &pll_param);
748 static int config_ddr_clk(u32 emi_clk)
751 s32 shift = 0, clk_sel, div = 1;
752 u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
753 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
755 if (emi_clk > MAX_DDR_CLK) {
756 printf("Warning:DDR clock should not exceed %d MHz\n",
757 MAX_DDR_CLK / SZ_DEC_1M);
758 emi_clk = MAX_DDR_CLK;
761 clk_src = get_periph_clk();
762 /* Find DDR clock input */
763 clk_sel = (cbcmr >> 10) & 0x3;
781 if ((clk_src % emi_clk) < 10000000)
782 div = clk_src / emi_clk;
784 div = (clk_src / emi_clk) + 1;
788 cbcdr = cbcdr & ~(0x7 << shift);
789 cbcdr |= ((div - 1) << shift);
790 __raw_writel(cbcdr, &mxc_ccm->cbcdr);
791 while (__raw_readl(&mxc_ccm->cdhipr) != 0)
793 __raw_writel(0x0, &mxc_ccm->ccdr);
799 * This function assumes the expected core clock has to be changed by
800 * modifying the PLL. This is NOT true always but for most of the times,
801 * it is. So it assumes the PLL output freq is the same as the expected
802 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
803 * In the latter case, it will try to increase the presc value until
804 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
805 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
806 * on the targeted PLL and reference input clock to the PLL. Lastly,
807 * it sets the register based on these values along with the dividers.
808 * Note 1) There is no value checking for the passed-in divider values
809 * so the caller has to make sure those values are sensible.
810 * 2) Also adjust the NFC divider such that the NFC clock doesn't
811 * exceed NFC_CLK_MAX.
812 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
813 * 177MHz for higher voltage, this function fixes the max to 133MHz.
814 * 4) This function should not have allowed diag_printf() calls since
815 * the serial driver has been stoped. But leave then here to allow
816 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
818 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
824 if (config_core_clk(ref, freq))
828 if (config_periph_clk(ref, freq))
832 if (config_ddr_clk(freq))
836 if (config_nfc_clk(freq))
840 printf("Warning:Unsupported or invalid clock type\n");
848 * The clock for the external interface can be set to use internal clock
849 * if fuse bank 4, row 3, bit 2 is set.
850 * This is an undocumented feature and it was confirmed by Freescale's support:
851 * Fuses (but not pins) may be used to configure SATA clocks.
852 * Particularly the i.MX53 Fuse_Map contains the next information
853 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
854 * '00' - 100MHz (External)
855 * '01' - 50MHz (External)
856 * '10' - 120MHz, internal (USB PHY)
859 void mxc_set_sata_internal_clock(void)
862 (u32 *)(IIM_BASE_ADDR + 0x180c);
866 writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
871 * Dump some core clockes.
873 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
877 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
878 printf("PLL1 %8d MHz\n", freq / 1000000);
879 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
880 printf("PLL2 %8d MHz\n", freq / 1000000);
881 freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
882 printf("PLL3 %8d MHz\n", freq / 1000000);
884 freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
885 printf("PLL4 %8d MHz\n", freq / 1000000);
889 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
890 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
891 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
892 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
897 /***************************************************/
900 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,