3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
43 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
44 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
45 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
46 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
48 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
52 #define AHB_CLK_ROOT 133333333
53 #define SZ_DEC_1M 1000000
54 #define PLL_PD_MAX 16 /* Actual pd+1 */
55 #define PLL_MFI_MAX 15
63 #define MX5_CBCMR 0x00015154
64 #define MX5_CBCDR 0x02888945
66 struct fixed_pll_mfd {
71 const struct fixed_pll_mfd fixed_mfd[] = {
82 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
83 #define PLL_FREQ_MIN(ref_clk) \
84 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
85 #define MAX_DDR_CLK 420000000
86 #define NFC_CLK_MAX 34000000
88 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
90 void set_usboh3_clk(void)
92 clrsetbits_le32(&mxc_ccm->cscmr1,
93 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
94 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
95 clrsetbits_le32(&mxc_ccm->cscdr1,
96 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
97 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
98 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
99 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
102 void enable_usboh3_clk(unsigned char enable)
105 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
107 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
110 #ifdef CONFIG_I2C_MXC
111 /* i2c_num can be from 0 - 2 */
112 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
118 mask = MXC_CCM_CCGR_CG_MASK <<
119 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
121 setbits_le32(&mxc_ccm->CCGR1, mask);
123 clrbits_le32(&mxc_ccm->CCGR1, mask);
128 void set_usb_phy1_clk(void)
130 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
133 void enable_usb_phy1_clk(unsigned char enable)
136 setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
138 clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
141 void set_usb_phy2_clk(void)
143 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
146 void enable_usb_phy2_clk(unsigned char enable)
149 setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
151 clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
155 * Calculate the frequency of PLLn.
157 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
159 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
160 uint64_t refclk, temp;
163 ctrl = readl(&pll->ctrl);
165 if (ctrl & MXC_DPLLC_CTL_HFSM) {
166 mfn = readl(&pll->hfs_mfn);
167 mfd = readl(&pll->hfs_mfd);
168 op = readl(&pll->hfs_op);
170 mfn = readl(&pll->mfn);
171 mfd = readl(&pll->mfd);
172 op = readl(&pll->op);
175 mfd &= MXC_DPLLC_MFD_MFD_MASK;
176 mfn &= MXC_DPLLC_MFN_MFN_MASK;
177 pdf = op & MXC_DPLLC_OP_PDF_MASK;
178 mfi = MXC_DPLLC_OP_MFI_RD(op);
185 if (mfn >= 0x04000000) {
192 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
195 do_div(refclk, pdf + 1);
196 temp = refclk * mfn_abs;
197 do_div(temp, mfd + 1);
211 u32 get_mcu_main_clk(void)
215 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
216 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
217 return freq / (reg + 1);
221 * Get the rate of peripheral's root clock.
223 u32 get_periph_clk(void)
227 reg = readl(&mxc_ccm->cbcdr);
228 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
229 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
230 reg = readl(&mxc_ccm->cbcmr);
231 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
233 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
235 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
243 * Get the rate of ipg clock.
245 static u32 get_ipg_clk(void)
247 uint32_t freq, reg, div;
249 freq = get_ahb_clk();
251 reg = readl(&mxc_ccm->cbcdr);
252 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
258 * Get the rate of ipg_per clock.
260 static u32 get_ipg_per_clk(void)
262 u32 pred1, pred2, podf;
264 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
265 return get_ipg_clk();
266 /* Fixme: not handle what about lpm*/
267 podf = readl(&mxc_ccm->cbcdr);
268 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
269 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
270 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
271 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
275 * Get the rate of uart clk.
277 static u32 get_uart_clk(void)
279 unsigned int freq, reg, pred, podf;
281 reg = readl(&mxc_ccm->cscmr1);
282 switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
284 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
287 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
290 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
296 reg = readl(&mxc_ccm->cscdr1);
297 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
298 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
299 freq /= (pred + 1) * (podf + 1);
305 * This function returns the low power audio clock.
307 static u32 get_lp_apm(void)
310 u32 ccsr = readl(&mxc_ccm->ccsr);
312 if (((ccsr >> 9) & 1) == 0)
315 ret_val = MXC_CLK32 * 1024;
321 * get cspi clock rate.
323 static u32 imx_get_cspiclk(void)
325 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
326 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
327 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
329 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
330 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
331 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
335 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
336 ((pre_pdf + 1) * (pdf + 1));
339 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
340 ((pre_pdf + 1) * (pdf + 1));
343 ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
344 ((pre_pdf + 1) * (pdf + 1));
347 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
354 static u32 get_axi_a_clk(void)
356 u32 cbcdr = readl(&mxc_ccm->cbcdr);
357 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
359 return get_periph_clk() / (pdf + 1);
362 static u32 get_axi_b_clk(void)
364 u32 cbcdr = readl(&mxc_ccm->cbcdr);
365 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
367 return get_periph_clk() / (pdf + 1);
370 static u32 get_emi_slow_clk(void)
372 u32 cbcdr = readl(&mxc_ccm->cbcdr);
373 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
374 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
377 return get_ahb_clk() / (pdf + 1);
379 return get_periph_clk() / (pdf + 1);
382 static u32 get_ddr_clk(void)
385 u32 cbcmr = readl(&mxc_ccm->cbcmr);
386 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
388 u32 cbcdr = readl(&mxc_ccm->cbcdr);
389 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
390 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
392 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
393 ret_val /= ddr_clk_podf + 1;
398 switch (ddr_clk_sel) {
400 ret_val = get_axi_a_clk();
403 ret_val = get_axi_b_clk();
406 ret_val = get_emi_slow_clk();
409 ret_val = get_ahb_clk();
419 * The API of get mxc clocks.
421 unsigned int mxc_get_clock(enum mxc_clock clk)
425 return get_mcu_main_clk();
427 return get_ahb_clk();
429 return get_ipg_clk();
432 return get_ipg_per_clk();
434 return get_uart_clk();
436 return imx_get_cspiclk();
438 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
440 return get_ahb_clk();
442 return get_ddr_clk();
449 u32 imx_get_uartclk(void)
451 return get_uart_clk();
455 u32 imx_get_fecclk(void)
457 return mxc_get_clock(MXC_IPG_CLK);
460 static int gcd(int m, int n)
475 * This is to calculate various parameters based on reference clock and
476 * targeted clock based on the equation:
477 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
478 * This calculation is based on a fixed MFD value for simplicity.
480 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
482 u64 pd, mfi = 1, mfn, mfd, t1;
483 u32 n_target = target;
487 * Make sure targeted freq is in the valid range.
488 * Otherwise the following calculation might be wrong!!!
490 if (n_target < PLL_FREQ_MIN(ref) ||
491 n_target > PLL_FREQ_MAX(ref)) {
492 printf("Targeted peripheral clock should be"
493 "within [%d - %d]\n",
494 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
495 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
499 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
500 if (fixed_mfd[i].ref_clk_hz == ref) {
501 mfd = fixed_mfd[i].mfd;
506 if (i == ARRAY_SIZE(fixed_mfd))
509 /* Use n_target and n_ref to avoid overflow */
510 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
512 do_div(t1, (4 * n_ref));
514 if (mfi > PLL_MFI_MAX)
521 * Now got pd and mfi already
523 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
531 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
532 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
546 #define calc_div(tgt_clk, src_clk, limit) ({ \
548 if (((src_clk) % (tgt_clk)) <= 100) \
549 v = (src_clk) / (tgt_clk); \
551 v = ((src_clk) / (tgt_clk)) + 1;\
557 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
559 writel(0x1232, &pll->ctrl); \
560 writel(0x2, &pll->config); \
561 writel((((pd) - 1) << 0) | ((fi) << 4), \
563 writel(fn, &(pll->mfn)); \
564 writel((fd) - 1, &pll->mfd); \
565 writel((((pd) - 1) << 0) | ((fi) << 4), \
567 writel(fn, &pll->hfs_mfn); \
568 writel((fd) - 1, &pll->hfs_mfd); \
569 writel(0x1232, &pll->ctrl); \
570 while (!readl(&pll->ctrl) & 0x1) \
574 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
576 u32 ccsr = readl(&mxc_ccm->ccsr);
577 struct mxc_pll_reg *pll = mxc_plls[index];
581 /* Switch ARM to PLL2 clock */
582 writel(ccsr | 0x4, &mxc_ccm->ccsr);
583 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
584 pll_param->mfi, pll_param->mfn,
587 writel(ccsr & ~0x4, &mxc_ccm->ccsr);
590 /* Switch to pll2 bypass clock */
591 writel(ccsr | 0x2, &mxc_ccm->ccsr);
592 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
593 pll_param->mfi, pll_param->mfn,
596 writel(ccsr & ~0x2, &mxc_ccm->ccsr);
599 /* Switch to pll3 bypass clock */
600 writel(ccsr | 0x1, &mxc_ccm->ccsr);
601 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
602 pll_param->mfi, pll_param->mfn,
605 writel(ccsr & ~0x1, &mxc_ccm->ccsr);
608 /* Switch to pll4 bypass clock */
609 writel(ccsr | 0x20, &mxc_ccm->ccsr);
610 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
611 pll_param->mfi, pll_param->mfn,
614 writel(ccsr & ~0x20, &mxc_ccm->ccsr);
623 /* Config CPU clock */
624 static int config_core_clk(u32 ref, u32 freq)
627 struct pll_param pll_param;
629 memset(&pll_param, 0, sizeof(struct pll_param));
631 /* The case that periph uses PLL1 is not considered here */
632 ret = calc_pll_params(ref, freq, &pll_param);
634 printf("Error:Can't find pll parameters: %d\n", ret);
638 return config_pll_clk(PLL1_CLOCK, &pll_param);
641 static int config_nfc_clk(u32 nfc_clk)
643 u32 parent_rate = get_emi_slow_clk();
644 u32 div = parent_rate / nfc_clk;
650 if (parent_rate / div > NFC_CLK_MAX)
652 clrsetbits_le32(&mxc_ccm->cbcdr,
653 MXC_CCM_CBCDR_NFC_PODF_MASK,
654 MXC_CCM_CBCDR_NFC_PODF(div - 1));
655 while (readl(&mxc_ccm->cdhipr) != 0)
660 /* Config main_bus_clock for periphs */
661 static int config_periph_clk(u32 ref, u32 freq)
664 struct pll_param pll_param;
666 memset(&pll_param, 0, sizeof(struct pll_param));
668 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
669 ret = calc_pll_params(ref, freq, &pll_param);
671 printf("Error:Can't find pll parameters: %d\n",
675 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
676 readl(&mxc_ccm->cbcmr))) {
678 return config_pll_clk(PLL1_CLOCK, &pll_param);
681 return config_pll_clk(PLL3_CLOCK, &pll_param);
691 static int config_ddr_clk(u32 emi_clk)
694 s32 shift = 0, clk_sel, div = 1;
695 u32 cbcmr = readl(&mxc_ccm->cbcmr);
697 if (emi_clk > MAX_DDR_CLK) {
698 printf("Warning:DDR clock should not exceed %d MHz\n",
699 MAX_DDR_CLK / SZ_DEC_1M);
700 emi_clk = MAX_DDR_CLK;
703 clk_src = get_periph_clk();
704 /* Find DDR clock input */
705 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
723 if ((clk_src % emi_clk) < 10000000)
724 div = clk_src / emi_clk;
726 div = (clk_src / emi_clk) + 1;
730 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
731 while (readl(&mxc_ccm->cdhipr) != 0)
733 writel(0x0, &mxc_ccm->ccdr);
739 * This function assumes the expected core clock has to be changed by
740 * modifying the PLL. This is NOT true always but for most of the times,
741 * it is. So it assumes the PLL output freq is the same as the expected
742 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
743 * In the latter case, it will try to increase the presc value until
744 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
745 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
746 * on the targeted PLL and reference input clock to the PLL. Lastly,
747 * it sets the register based on these values along with the dividers.
748 * Note 1) There is no value checking for the passed-in divider values
749 * so the caller has to make sure those values are sensible.
750 * 2) Also adjust the NFC divider such that the NFC clock doesn't
751 * exceed NFC_CLK_MAX.
752 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
753 * 177MHz for higher voltage, this function fixes the max to 133MHz.
754 * 4) This function should not have allowed diag_printf() calls since
755 * the serial driver has been stoped. But leave then here to allow
756 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
758 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
764 if (config_core_clk(ref, freq))
768 if (config_periph_clk(ref, freq))
772 if (config_ddr_clk(freq))
776 if (config_nfc_clk(freq))
780 printf("Warning:Unsupported or invalid clock type\n");
788 * The clock for the external interface can be set to use internal clock
789 * if fuse bank 4, row 3, bit 2 is set.
790 * This is an undocumented feature and it was confirmed by Freescale's support:
791 * Fuses (but not pins) may be used to configure SATA clocks.
792 * Particularly the i.MX53 Fuse_Map contains the next information
793 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
794 * '00' - 100MHz (External)
795 * '01' - 50MHz (External)
796 * '10' - 120MHz, internal (USB PHY)
799 void mxc_set_sata_internal_clock(void)
802 (u32 *)(IIM_BASE_ADDR + 0x180c);
806 clrsetbits_le32(tmp_base, 0x6, 0x4);
811 * Dump some core clockes.
813 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
817 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
818 printf("PLL1 %8d MHz\n", freq / 1000000);
819 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
820 printf("PLL2 %8d MHz\n", freq / 1000000);
821 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
822 printf("PLL3 %8d MHz\n", freq / 1000000);
824 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
825 printf("PLL4 %8d MHz\n", freq / 1000000);
829 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
830 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
831 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
832 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
837 /***************************************************/
840 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,