3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
43 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
44 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
45 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
46 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
48 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
52 #define AHB_CLK_ROOT 133333333
53 #define SZ_DEC_1M 1000000
54 #define PLL_PD_MAX 16 /* Actual pd+1 */
55 #define PLL_MFI_MAX 15
63 #define MX5_CBCMR 0x00015154
64 #define MX5_CBCDR 0x02888945
66 struct fixed_pll_mfd {
71 const struct fixed_pll_mfd fixed_mfd[] = {
82 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
83 #define PLL_FREQ_MIN(ref_clk) \
84 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
85 #define MAX_DDR_CLK 420000000
86 #define NFC_CLK_MAX 34000000
88 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
90 void set_usboh3_clk(void)
94 reg = readl(&mxc_ccm->cscmr1) &
95 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
96 reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
97 writel(reg, &mxc_ccm->cscmr1);
99 reg = readl(&mxc_ccm->cscdr1);
100 reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
101 reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
102 reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
103 reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
105 writel(reg, &mxc_ccm->cscdr1);
108 void enable_usboh3_clk(unsigned char enable)
112 reg = readl(&mxc_ccm->CCGR2);
114 reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
116 reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
117 writel(reg, &mxc_ccm->CCGR2);
120 #ifdef CONFIG_I2C_MXC
121 /* i2c_num can be from 0 - 2 */
122 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
129 mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
130 reg = __raw_readl(&mxc_ccm->CCGR1);
135 __raw_writel(reg, &mxc_ccm->CCGR1);
140 void set_usb_phy1_clk(void)
144 reg = readl(&mxc_ccm->cscmr1);
145 reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
146 writel(reg, &mxc_ccm->cscmr1);
149 void enable_usb_phy1_clk(unsigned char enable)
153 reg = readl(&mxc_ccm->CCGR4);
155 reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
157 reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
158 writel(reg, &mxc_ccm->CCGR4);
161 void set_usb_phy2_clk(void)
165 reg = readl(&mxc_ccm->cscmr1);
166 reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
167 writel(reg, &mxc_ccm->cscmr1);
170 void enable_usb_phy2_clk(unsigned char enable)
174 reg = readl(&mxc_ccm->CCGR4);
176 reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
178 reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
179 writel(reg, &mxc_ccm->CCGR4);
183 * Calculate the frequency of PLLn.
185 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
187 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
188 uint64_t refclk, temp;
191 ctrl = readl(&pll->ctrl);
193 if (ctrl & MXC_DPLLC_CTL_HFSM) {
194 mfn = __raw_readl(&pll->hfs_mfn);
195 mfd = __raw_readl(&pll->hfs_mfd);
196 op = __raw_readl(&pll->hfs_op);
198 mfn = __raw_readl(&pll->mfn);
199 mfd = __raw_readl(&pll->mfd);
200 op = __raw_readl(&pll->op);
203 mfd &= MXC_DPLLC_MFD_MFD_MASK;
204 mfn &= MXC_DPLLC_MFN_MFN_MASK;
205 pdf = op & MXC_DPLLC_OP_PDF_MASK;
206 mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
213 if (mfn >= 0x04000000) {
220 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
223 do_div(refclk, pdf + 1);
224 temp = refclk * mfn_abs;
225 do_div(temp, mfd + 1);
239 u32 get_mcu_main_clk(void)
243 reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
244 MXC_CCM_CACRR_ARM_PODF_OFFSET;
245 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
246 return freq / (reg + 1);
250 * Get the rate of peripheral's root clock.
252 u32 get_periph_clk(void)
256 reg = __raw_readl(&mxc_ccm->cbcdr);
257 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
258 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
259 reg = __raw_readl(&mxc_ccm->cbcmr);
260 switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
261 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
263 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
265 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
273 * Get the rate of ipg clock.
275 static u32 get_ipg_clk(void)
277 uint32_t freq, reg, div;
279 freq = get_ahb_clk();
281 reg = __raw_readl(&mxc_ccm->cbcdr);
282 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
283 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
289 * Get the rate of ipg_per clock.
291 static u32 get_ipg_per_clk(void)
293 u32 pred1, pred2, podf;
295 if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
296 return get_ipg_clk();
297 /* Fixme: not handle what about lpm*/
298 podf = __raw_readl(&mxc_ccm->cbcdr);
299 pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
300 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
301 pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
302 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
303 podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
304 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
306 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
310 * Get the rate of uart clk.
312 static u32 get_uart_clk(void)
314 unsigned int freq, reg, pred, podf;
316 reg = __raw_readl(&mxc_ccm->cscmr1);
317 switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
318 MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
320 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
323 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
326 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
332 reg = __raw_readl(&mxc_ccm->cscdr1);
334 pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
335 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
337 podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
338 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
339 freq /= (pred + 1) * (podf + 1);
345 * This function returns the low power audio clock.
347 static u32 get_lp_apm(void)
350 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
352 if (((ccsr >> 9) & 1) == 0)
355 ret_val = MXC_CLK32 * 1024;
361 * get cspi clock rate.
363 static u32 imx_get_cspiclk(void)
365 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
366 u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
367 u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
369 pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
370 >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
371 pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
372 >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
373 clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
374 >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
378 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
379 ((pre_pdf + 1) * (pdf + 1));
382 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
383 ((pre_pdf + 1) * (pdf + 1));
386 ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
387 ((pre_pdf + 1) * (pdf + 1));
390 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
397 static u32 get_axi_a_clk(void)
399 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
400 u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
401 >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
403 return get_periph_clk() / (pdf + 1);
406 static u32 get_axi_b_clk(void)
408 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
409 u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
410 >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
412 return get_periph_clk() / (pdf + 1);
415 static u32 get_emi_slow_clk(void)
417 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
418 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
419 u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
420 >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
423 return get_ahb_clk() / (pdf + 1);
425 return get_periph_clk() / (pdf + 1);
428 static u32 get_ddr_clk(void)
431 u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
432 u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
433 >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
435 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
436 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
437 u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
438 MXC_CCM_CBCDR_DDR_PODF_OFFSET;
440 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
441 ret_val /= ddr_clk_podf + 1;
446 switch (ddr_clk_sel) {
448 ret_val = get_axi_a_clk();
451 ret_val = get_axi_b_clk();
454 ret_val = get_emi_slow_clk();
457 ret_val = get_ahb_clk();
467 * The API of get mxc clocks.
469 unsigned int mxc_get_clock(enum mxc_clock clk)
473 return get_mcu_main_clk();
475 return get_ahb_clk();
477 return get_ipg_clk();
480 return get_ipg_per_clk();
482 return get_uart_clk();
484 return imx_get_cspiclk();
486 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
488 return get_ahb_clk();
490 return get_ddr_clk();
497 u32 imx_get_uartclk(void)
499 return get_uart_clk();
503 u32 imx_get_fecclk(void)
505 return mxc_get_clock(MXC_IPG_CLK);
508 static int gcd(int m, int n)
523 * This is to calculate various parameters based on reference clock and
524 * targeted clock based on the equation:
525 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
526 * This calculation is based on a fixed MFD value for simplicity.
528 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
530 u64 pd, mfi = 1, mfn, mfd, t1;
531 u32 n_target = target;
535 * Make sure targeted freq is in the valid range.
536 * Otherwise the following calculation might be wrong!!!
538 if (n_target < PLL_FREQ_MIN(ref) ||
539 n_target > PLL_FREQ_MAX(ref)) {
540 printf("Targeted peripheral clock should be"
541 "within [%d - %d]\n",
542 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
543 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
547 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
548 if (fixed_mfd[i].ref_clk_hz == ref) {
549 mfd = fixed_mfd[i].mfd;
554 if (i == ARRAY_SIZE(fixed_mfd))
557 /* Use n_target and n_ref to avoid overflow */
558 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
560 do_div(t1, (4 * n_ref));
562 if (mfi > PLL_MFI_MAX)
569 * Now got pd and mfi already
571 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
579 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
580 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
594 #define calc_div(tgt_clk, src_clk, limit) ({ \
596 if (((src_clk) % (tgt_clk)) <= 100) \
597 v = (src_clk) / (tgt_clk); \
599 v = ((src_clk) / (tgt_clk)) + 1;\
605 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
607 __raw_writel(0x1232, &pll->ctrl); \
608 __raw_writel(0x2, &pll->config); \
609 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
611 __raw_writel(fn, &(pll->mfn)); \
612 __raw_writel((fd) - 1, &pll->mfd); \
613 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
615 __raw_writel(fn, &pll->hfs_mfn); \
616 __raw_writel((fd) - 1, &pll->hfs_mfd); \
617 __raw_writel(0x1232, &pll->ctrl); \
618 while (!__raw_readl(&pll->ctrl) & 0x1) \
622 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
624 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
625 struct mxc_pll_reg *pll = mxc_plls[index];
629 /* Switch ARM to PLL2 clock */
630 __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
631 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
632 pll_param->mfi, pll_param->mfn,
635 __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
638 /* Switch to pll2 bypass clock */
639 __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
640 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
641 pll_param->mfi, pll_param->mfn,
644 __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
647 /* Switch to pll3 bypass clock */
648 __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
649 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
650 pll_param->mfi, pll_param->mfn,
653 __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
656 /* Switch to pll4 bypass clock */
657 __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
658 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
659 pll_param->mfi, pll_param->mfn,
662 __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
671 /* Config CPU clock */
672 static int config_core_clk(u32 ref, u32 freq)
675 struct pll_param pll_param;
677 memset(&pll_param, 0, sizeof(struct pll_param));
679 /* The case that periph uses PLL1 is not considered here */
680 ret = calc_pll_params(ref, freq, &pll_param);
682 printf("Error:Can't find pll parameters: %d\n", ret);
686 return config_pll_clk(PLL1_CLOCK, &pll_param);
689 static int config_nfc_clk(u32 nfc_clk)
692 u32 parent_rate = get_emi_slow_clk();
693 u32 div = parent_rate / nfc_clk;
699 if (parent_rate / div > NFC_CLK_MAX)
701 reg = __raw_readl(&mxc_ccm->cbcdr);
702 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
703 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
704 __raw_writel(reg, &mxc_ccm->cbcdr);
705 while (__raw_readl(&mxc_ccm->cdhipr) != 0)
710 /* Config main_bus_clock for periphs */
711 static int config_periph_clk(u32 ref, u32 freq)
714 struct pll_param pll_param;
716 memset(&pll_param, 0, sizeof(struct pll_param));
718 if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
719 ret = calc_pll_params(ref, freq, &pll_param);
721 printf("Error:Can't find pll parameters: %d\n",
725 switch ((__raw_readl(&mxc_ccm->cbcmr) & \
726 MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
727 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
729 return config_pll_clk(PLL1_CLOCK, &pll_param);
732 return config_pll_clk(PLL3_CLOCK, &pll_param);
742 static int config_ddr_clk(u32 emi_clk)
745 s32 shift = 0, clk_sel, div = 1;
746 u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
747 u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
749 if (emi_clk > MAX_DDR_CLK) {
750 printf("Warning:DDR clock should not exceed %d MHz\n",
751 MAX_DDR_CLK / SZ_DEC_1M);
752 emi_clk = MAX_DDR_CLK;
755 clk_src = get_periph_clk();
756 /* Find DDR clock input */
757 clk_sel = (cbcmr >> 10) & 0x3;
775 if ((clk_src % emi_clk) < 10000000)
776 div = clk_src / emi_clk;
778 div = (clk_src / emi_clk) + 1;
782 cbcdr = cbcdr & ~(0x7 << shift);
783 cbcdr |= ((div - 1) << shift);
784 __raw_writel(cbcdr, &mxc_ccm->cbcdr);
785 while (__raw_readl(&mxc_ccm->cdhipr) != 0)
787 __raw_writel(0x0, &mxc_ccm->ccdr);
793 * This function assumes the expected core clock has to be changed by
794 * modifying the PLL. This is NOT true always but for most of the times,
795 * it is. So it assumes the PLL output freq is the same as the expected
796 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
797 * In the latter case, it will try to increase the presc value until
798 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
799 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
800 * on the targeted PLL and reference input clock to the PLL. Lastly,
801 * it sets the register based on these values along with the dividers.
802 * Note 1) There is no value checking for the passed-in divider values
803 * so the caller has to make sure those values are sensible.
804 * 2) Also adjust the NFC divider such that the NFC clock doesn't
805 * exceed NFC_CLK_MAX.
806 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
807 * 177MHz for higher voltage, this function fixes the max to 133MHz.
808 * 4) This function should not have allowed diag_printf() calls since
809 * the serial driver has been stoped. But leave then here to allow
810 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
812 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
818 if (config_core_clk(ref, freq))
822 if (config_periph_clk(ref, freq))
826 if (config_ddr_clk(freq))
830 if (config_nfc_clk(freq))
834 printf("Warning:Unsupported or invalid clock type\n");
842 * The clock for the external interface can be set to use internal clock
843 * if fuse bank 4, row 3, bit 2 is set.
844 * This is an undocumented feature and it was confirmed by Freescale's support:
845 * Fuses (but not pins) may be used to configure SATA clocks.
846 * Particularly the i.MX53 Fuse_Map contains the next information
847 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
848 * '00' - 100MHz (External)
849 * '01' - 50MHz (External)
850 * '10' - 120MHz, internal (USB PHY)
853 void mxc_set_sata_internal_clock(void)
856 (u32 *)(IIM_BASE_ADDR + 0x180c);
860 writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
865 * Dump some core clockes.
867 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
871 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
872 printf("PLL1 %8d MHz\n", freq / 1000000);
873 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
874 printf("PLL2 %8d MHz\n", freq / 1000000);
875 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
876 printf("PLL3 %8d MHz\n", freq / 1000000);
878 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
879 printf("PLL4 %8d MHz\n", freq / 1000000);
883 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
884 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
885 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
886 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
891 /***************************************************/
894 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,