3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
43 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
44 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
45 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
46 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
48 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
52 #define AHB_CLK_ROOT 133333333
53 #define SZ_DEC_1M 1000000
54 #define PLL_PD_MAX 16 /* Actual pd+1 */
55 #define PLL_MFI_MAX 15
63 #define MX5_CBCMR 0x00015154
64 #define MX5_CBCDR 0x02888945
66 struct fixed_pll_mfd {
71 const struct fixed_pll_mfd fixed_mfd[] = {
82 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
83 #define PLL_FREQ_MIN(ref_clk) \
84 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
85 #define MAX_DDR_CLK 420000000
86 #define NFC_CLK_MAX 34000000
88 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
90 void set_usboh3_clk(void)
92 clrsetbits_le32(&mxc_ccm->cscmr1,
93 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
94 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
95 clrsetbits_le32(&mxc_ccm->cscdr1,
96 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
97 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
98 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
99 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
102 void enable_usboh3_clk(unsigned char enable)
105 setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
107 clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
110 #ifdef CONFIG_I2C_MXC
111 /* i2c_num can be from 0 - 2 */
112 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
118 mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
120 setbits_le32(&mxc_ccm->CCGR1, mask);
122 clrbits_le32(&mxc_ccm->CCGR1, mask);
127 void set_usb_phy1_clk(void)
129 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
132 void enable_usb_phy1_clk(unsigned char enable)
135 setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
137 clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
140 void set_usb_phy2_clk(void)
142 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
145 void enable_usb_phy2_clk(unsigned char enable)
148 setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
150 clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
154 * Calculate the frequency of PLLn.
156 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
158 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
159 uint64_t refclk, temp;
162 ctrl = readl(&pll->ctrl);
164 if (ctrl & MXC_DPLLC_CTL_HFSM) {
165 mfn = readl(&pll->hfs_mfn);
166 mfd = readl(&pll->hfs_mfd);
167 op = readl(&pll->hfs_op);
169 mfn = readl(&pll->mfn);
170 mfd = readl(&pll->mfd);
171 op = readl(&pll->op);
174 mfd &= MXC_DPLLC_MFD_MFD_MASK;
175 mfn &= MXC_DPLLC_MFN_MFN_MASK;
176 pdf = op & MXC_DPLLC_OP_PDF_MASK;
177 mfi = MXC_DPLLC_OP_MFI_RD(op);
184 if (mfn >= 0x04000000) {
191 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
194 do_div(refclk, pdf + 1);
195 temp = refclk * mfn_abs;
196 do_div(temp, mfd + 1);
210 u32 get_mcu_main_clk(void)
214 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
215 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
216 return freq / (reg + 1);
220 * Get the rate of peripheral's root clock.
222 u32 get_periph_clk(void)
226 reg = readl(&mxc_ccm->cbcdr);
227 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
228 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
229 reg = readl(&mxc_ccm->cbcmr);
230 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
232 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
234 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
242 * Get the rate of ipg clock.
244 static u32 get_ipg_clk(void)
246 uint32_t freq, reg, div;
248 freq = get_ahb_clk();
250 reg = readl(&mxc_ccm->cbcdr);
251 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
257 * Get the rate of ipg_per clock.
259 static u32 get_ipg_per_clk(void)
261 u32 pred1, pred2, podf;
263 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
264 return get_ipg_clk();
265 /* Fixme: not handle what about lpm*/
266 podf = readl(&mxc_ccm->cbcdr);
267 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
268 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
269 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
270 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
274 * Get the rate of uart clk.
276 static u32 get_uart_clk(void)
278 unsigned int freq, reg, pred, podf;
280 reg = readl(&mxc_ccm->cscmr1);
281 switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
283 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
286 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
289 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
295 reg = readl(&mxc_ccm->cscdr1);
296 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
297 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
298 freq /= (pred + 1) * (podf + 1);
304 * This function returns the low power audio clock.
306 static u32 get_lp_apm(void)
309 u32 ccsr = readl(&mxc_ccm->ccsr);
311 if (((ccsr >> 9) & 1) == 0)
314 ret_val = MXC_CLK32 * 1024;
320 * get cspi clock rate.
322 static u32 imx_get_cspiclk(void)
324 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
325 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
326 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
328 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
329 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
330 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
334 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
335 ((pre_pdf + 1) * (pdf + 1));
338 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
339 ((pre_pdf + 1) * (pdf + 1));
342 ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
343 ((pre_pdf + 1) * (pdf + 1));
346 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
353 static u32 get_axi_a_clk(void)
355 u32 cbcdr = readl(&mxc_ccm->cbcdr);
356 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
358 return get_periph_clk() / (pdf + 1);
361 static u32 get_axi_b_clk(void)
363 u32 cbcdr = readl(&mxc_ccm->cbcdr);
364 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
366 return get_periph_clk() / (pdf + 1);
369 static u32 get_emi_slow_clk(void)
371 u32 cbcdr = readl(&mxc_ccm->cbcdr);
372 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
373 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
376 return get_ahb_clk() / (pdf + 1);
378 return get_periph_clk() / (pdf + 1);
381 static u32 get_ddr_clk(void)
384 u32 cbcmr = readl(&mxc_ccm->cbcmr);
385 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
387 u32 cbcdr = readl(&mxc_ccm->cbcdr);
388 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
389 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
391 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
392 ret_val /= ddr_clk_podf + 1;
397 switch (ddr_clk_sel) {
399 ret_val = get_axi_a_clk();
402 ret_val = get_axi_b_clk();
405 ret_val = get_emi_slow_clk();
408 ret_val = get_ahb_clk();
418 * The API of get mxc clocks.
420 unsigned int mxc_get_clock(enum mxc_clock clk)
424 return get_mcu_main_clk();
426 return get_ahb_clk();
428 return get_ipg_clk();
431 return get_ipg_per_clk();
433 return get_uart_clk();
435 return imx_get_cspiclk();
437 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
439 return get_ahb_clk();
441 return get_ddr_clk();
448 u32 imx_get_uartclk(void)
450 return get_uart_clk();
454 u32 imx_get_fecclk(void)
456 return mxc_get_clock(MXC_IPG_CLK);
459 static int gcd(int m, int n)
474 * This is to calculate various parameters based on reference clock and
475 * targeted clock based on the equation:
476 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
477 * This calculation is based on a fixed MFD value for simplicity.
479 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
481 u64 pd, mfi = 1, mfn, mfd, t1;
482 u32 n_target = target;
486 * Make sure targeted freq is in the valid range.
487 * Otherwise the following calculation might be wrong!!!
489 if (n_target < PLL_FREQ_MIN(ref) ||
490 n_target > PLL_FREQ_MAX(ref)) {
491 printf("Targeted peripheral clock should be"
492 "within [%d - %d]\n",
493 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
494 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
498 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
499 if (fixed_mfd[i].ref_clk_hz == ref) {
500 mfd = fixed_mfd[i].mfd;
505 if (i == ARRAY_SIZE(fixed_mfd))
508 /* Use n_target and n_ref to avoid overflow */
509 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
511 do_div(t1, (4 * n_ref));
513 if (mfi > PLL_MFI_MAX)
520 * Now got pd and mfi already
522 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
530 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
531 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
545 #define calc_div(tgt_clk, src_clk, limit) ({ \
547 if (((src_clk) % (tgt_clk)) <= 100) \
548 v = (src_clk) / (tgt_clk); \
550 v = ((src_clk) / (tgt_clk)) + 1;\
556 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
558 writel(0x1232, &pll->ctrl); \
559 writel(0x2, &pll->config); \
560 writel((((pd) - 1) << 0) | ((fi) << 4), \
562 writel(fn, &(pll->mfn)); \
563 writel((fd) - 1, &pll->mfd); \
564 writel((((pd) - 1) << 0) | ((fi) << 4), \
566 writel(fn, &pll->hfs_mfn); \
567 writel((fd) - 1, &pll->hfs_mfd); \
568 writel(0x1232, &pll->ctrl); \
569 while (!readl(&pll->ctrl) & 0x1) \
573 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
575 u32 ccsr = readl(&mxc_ccm->ccsr);
576 struct mxc_pll_reg *pll = mxc_plls[index];
580 /* Switch ARM to PLL2 clock */
581 writel(ccsr | 0x4, &mxc_ccm->ccsr);
582 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
583 pll_param->mfi, pll_param->mfn,
586 writel(ccsr & ~0x4, &mxc_ccm->ccsr);
589 /* Switch to pll2 bypass clock */
590 writel(ccsr | 0x2, &mxc_ccm->ccsr);
591 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
592 pll_param->mfi, pll_param->mfn,
595 writel(ccsr & ~0x2, &mxc_ccm->ccsr);
598 /* Switch to pll3 bypass clock */
599 writel(ccsr | 0x1, &mxc_ccm->ccsr);
600 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
601 pll_param->mfi, pll_param->mfn,
604 writel(ccsr & ~0x1, &mxc_ccm->ccsr);
607 /* Switch to pll4 bypass clock */
608 writel(ccsr | 0x20, &mxc_ccm->ccsr);
609 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
610 pll_param->mfi, pll_param->mfn,
613 writel(ccsr & ~0x20, &mxc_ccm->ccsr);
622 /* Config CPU clock */
623 static int config_core_clk(u32 ref, u32 freq)
626 struct pll_param pll_param;
628 memset(&pll_param, 0, sizeof(struct pll_param));
630 /* The case that periph uses PLL1 is not considered here */
631 ret = calc_pll_params(ref, freq, &pll_param);
633 printf("Error:Can't find pll parameters: %d\n", ret);
637 return config_pll_clk(PLL1_CLOCK, &pll_param);
640 static int config_nfc_clk(u32 nfc_clk)
642 u32 parent_rate = get_emi_slow_clk();
643 u32 div = parent_rate / nfc_clk;
649 if (parent_rate / div > NFC_CLK_MAX)
651 clrsetbits_le32(&mxc_ccm->cbcdr,
652 MXC_CCM_CBCDR_NFC_PODF_MASK,
653 MXC_CCM_CBCDR_NFC_PODF(div - 1));
654 while (readl(&mxc_ccm->cdhipr) != 0)
659 /* Config main_bus_clock for periphs */
660 static int config_periph_clk(u32 ref, u32 freq)
663 struct pll_param pll_param;
665 memset(&pll_param, 0, sizeof(struct pll_param));
667 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
668 ret = calc_pll_params(ref, freq, &pll_param);
670 printf("Error:Can't find pll parameters: %d\n",
674 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
675 readl(&mxc_ccm->cbcmr))) {
677 return config_pll_clk(PLL1_CLOCK, &pll_param);
680 return config_pll_clk(PLL3_CLOCK, &pll_param);
690 static int config_ddr_clk(u32 emi_clk)
693 s32 shift = 0, clk_sel, div = 1;
694 u32 cbcmr = readl(&mxc_ccm->cbcmr);
696 if (emi_clk > MAX_DDR_CLK) {
697 printf("Warning:DDR clock should not exceed %d MHz\n",
698 MAX_DDR_CLK / SZ_DEC_1M);
699 emi_clk = MAX_DDR_CLK;
702 clk_src = get_periph_clk();
703 /* Find DDR clock input */
704 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
722 if ((clk_src % emi_clk) < 10000000)
723 div = clk_src / emi_clk;
725 div = (clk_src / emi_clk) + 1;
729 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
730 while (readl(&mxc_ccm->cdhipr) != 0)
732 writel(0x0, &mxc_ccm->ccdr);
738 * This function assumes the expected core clock has to be changed by
739 * modifying the PLL. This is NOT true always but for most of the times,
740 * it is. So it assumes the PLL output freq is the same as the expected
741 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
742 * In the latter case, it will try to increase the presc value until
743 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
744 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
745 * on the targeted PLL and reference input clock to the PLL. Lastly,
746 * it sets the register based on these values along with the dividers.
747 * Note 1) There is no value checking for the passed-in divider values
748 * so the caller has to make sure those values are sensible.
749 * 2) Also adjust the NFC divider such that the NFC clock doesn't
750 * exceed NFC_CLK_MAX.
751 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
752 * 177MHz for higher voltage, this function fixes the max to 133MHz.
753 * 4) This function should not have allowed diag_printf() calls since
754 * the serial driver has been stoped. But leave then here to allow
755 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
757 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
763 if (config_core_clk(ref, freq))
767 if (config_periph_clk(ref, freq))
771 if (config_ddr_clk(freq))
775 if (config_nfc_clk(freq))
779 printf("Warning:Unsupported or invalid clock type\n");
787 * The clock for the external interface can be set to use internal clock
788 * if fuse bank 4, row 3, bit 2 is set.
789 * This is an undocumented feature and it was confirmed by Freescale's support:
790 * Fuses (but not pins) may be used to configure SATA clocks.
791 * Particularly the i.MX53 Fuse_Map contains the next information
792 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
793 * '00' - 100MHz (External)
794 * '01' - 50MHz (External)
795 * '10' - 120MHz, internal (USB PHY)
798 void mxc_set_sata_internal_clock(void)
801 (u32 *)(IIM_BASE_ADDR + 0x180c);
805 clrsetbits_le32(tmp_base, 0x6, 0x4);
810 * Dump some core clockes.
812 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
816 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
817 printf("PLL1 %8d MHz\n", freq / 1000000);
818 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
819 printf("PLL2 %8d MHz\n", freq / 1000000);
820 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
821 printf("PLL3 %8d MHz\n", freq / 1000000);
823 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
824 printf("PLL4 %8d MHz\n", freq / 1000000);
828 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
829 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
830 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
831 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
836 /***************************************************/
839 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,