2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <generated/asm-offsets.h>
25 #include <linux/linkage.h>
27 .section ".text.init", "x"
29 .macro init_arm_erratum
30 /* ARM erratum ID #468414 */
31 mrc 15, 0, r1, c1, c0, 1
32 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
33 mcr 15, 0, r1, c1, c0, 1
37 * L2CC Cache setup/invalidation/disable
40 /* explicitly disable L2 cache */
41 mrc 15, 0, r0, c1, c0, 1
43 mcr 15, 0, r0, c1, c0, 1
45 /* reconfigure L2 cache aux control reg */
46 ldr r0, =0xC0 | /* tag RAM */ \
47 0x4 | /* data RAM */ \
48 1 << 24 | /* disable write allocate delay */ \
49 1 << 23 | /* disable write allocate combine */ \
50 1 << 22 /* disable write allocate */
52 #if defined(CONFIG_MX51)
53 ldr r3, [r4, #ROM_SI_REV]
56 /* disable write combine for TO 2 and lower revs */
57 orrls r0, r0, #1 << 25
60 mcr 15, 1, r0, c9, c0, 2
63 /* AIPS setup - Only setup MPROTx registers.
64 * The PACR default values are good.*/
67 * Set all MPROTx to be non-bufferable, trusted for R/W,
68 * not forced to user-mode.
70 ldr r0, =AIPS1_BASE_ADDR
74 ldr r0, =AIPS2_BASE_ADDR
78 * Clear the on and off peripheral modules Supervisor Protect bit
79 * for SDMA to access them. Did not change the AIPS control registers
80 * (offset 0x20) access type
87 /* VPU and IPU given higher priority (0x4)
88 * IPU accesses with ID=0x1 given highest priority (=0xA)
90 ldr r0, =M4IF_BASE_ADDR
104 .endm /* init_m4if */
106 .macro setup_pll pll, freq
118 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
120 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
122 ldr r1, [r2, #W_DP_OP]
123 str r1, [r0, #PLL_DP_OP]
124 str r1, [r0, #PLL_DP_HFS_OP]
126 ldr r1, [r2, #W_DP_MFD]
127 str r1, [r0, #PLL_DP_MFD]
128 str r1, [r0, #PLL_DP_HFS_MFD]
130 ldr r1, [r2, #W_DP_MFN]
131 str r1, [r0, #PLL_DP_MFN]
132 str r1, [r0, #PLL_DP_HFS_MFN]
135 str r1, [r0, #PLL_DP_CTL]
136 1: ldr r1, [r0, #PLL_DP_CTL]
140 /* r10 saved upper lr */
143 .macro setup_pll_errata pll, freq
145 str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
147 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
148 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
153 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
154 str r5, [r2, #PLL_DP_HFS_MFN]
157 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
159 2: ldr r1, [r2, #PLL_DP_CONFIG]
163 ldr r1, =100 /* Wait at least 4 us */
168 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
172 #if defined (CONFIG_MX51)
173 ldr r0, =CCM_BASE_ADDR
175 /* Gate of clocks to the peripherals first */
177 str r1, [r0, #CLKCTL_CCGR0]
178 str r4, [r0, #CLKCTL_CCGR1]
179 str r4, [r0, #CLKCTL_CCGR2]
180 str r4, [r0, #CLKCTL_CCGR3]
183 str r1, [r0, #CLKCTL_CCGR4]
185 str r1, [r0, #CLKCTL_CCGR5]
187 str r1, [r0, #CLKCTL_CCGR6]
189 /* Disable IPU and HSC dividers */
191 str r1, [r0, #CLKCTL_CCDR]
193 /* Make sure to switch the DDR away from PLL 1 */
195 str r1, [r0, #CLKCTL_CBCDR]
196 /* make sure divider effective */
197 1: ldr r1, [r0, #CLKCTL_CDHIPR]
201 /* Switch ARM to step clock */
203 str r1, [r0, #CLKCTL_CCSR]
205 #if defined(CONFIG_MX51_PLL_ERRATA)
206 setup_pll PLL1_BASE_ADDR, 864
207 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
209 setup_pll PLL1_BASE_ADDR, 800
212 setup_pll PLL3_BASE_ADDR, 665
214 /* Switch peripheral to PLL 3 */
215 ldr r0, =CCM_BASE_ADDR
216 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
217 str r1, [r0, #CLKCTL_CBCMR]
219 str r1, [r0, #CLKCTL_CBCDR]
220 setup_pll PLL2_BASE_ADDR, 665
222 /* Switch peripheral to PLL2 */
223 ldr r0, =CCM_BASE_ADDR
225 str r1, [r0, #CLKCTL_CBCDR]
226 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
227 str r1, [r0, #CLKCTL_CBCMR]
229 setup_pll PLL3_BASE_ADDR, 216
231 /* Set the platform clock dividers */
232 ldr r0, =ARM_BASE_ADDR
236 ldr r0, =CCM_BASE_ADDR
238 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
239 ldr r3, [r4, #ROM_SI_REV]
244 str r1, [r0, #CLKCTL_CACRR]
246 /* Switch ARM back to PLL 1 */
247 str r4, [r0, #CLKCTL_CCSR]
250 /* Use lp_apm (24MHz) source for perclk */
251 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
252 str r1, [r0, #CLKCTL_CBCMR]
253 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
254 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
255 str r1, [r0, #CLKCTL_CBCDR]
257 /* Restore the default values in the Gate registers */
259 str r1, [r0, #CLKCTL_CCGR0]
260 str r1, [r0, #CLKCTL_CCGR1]
261 str r1, [r0, #CLKCTL_CCGR2]
262 str r1, [r0, #CLKCTL_CCGR3]
263 str r1, [r0, #CLKCTL_CCGR4]
264 str r1, [r0, #CLKCTL_CCGR5]
265 str r1, [r0, #CLKCTL_CCGR6]
267 /* Use PLL 2 for UART's, get 66.5MHz from it */
269 str r1, [r0, #CLKCTL_CSCMR1]
271 str r1, [r0, #CLKCTL_CSCDR1]
272 /* make sure divider effective */
273 1: ldr r1, [r0, #CLKCTL_CDHIPR]
277 str r4, [r0, #CLKCTL_CCDR]
279 /* for cko - for ARM div by 8 */
281 add r1, r1, #0x00000F0
282 str r1, [r0, #CLKCTL_CCOSR]
283 #else /* CONFIG_MX53 */
284 ldr r0, =CCM_BASE_ADDR
286 /* Gate of clocks to the peripherals first */
288 str r1, [r0, #CLKCTL_CCGR0]
289 str r4, [r0, #CLKCTL_CCGR1]
290 str r4, [r0, #CLKCTL_CCGR2]
291 str r4, [r0, #CLKCTL_CCGR3]
292 str r4, [r0, #CLKCTL_CCGR7]
294 str r1, [r0, #CLKCTL_CCGR4]
296 str r1, [r0, #CLKCTL_CCGR5]
298 str r1, [r0, #CLKCTL_CCGR6]
300 /* Switch ARM to step clock */
302 str r1, [r0, #CLKCTL_CCSR]
304 setup_pll PLL1_BASE_ADDR, 800
306 setup_pll PLL3_BASE_ADDR, 400
308 /* Switch peripheral to PLL3 */
309 ldr r0, =CCM_BASE_ADDR
311 str r1, [r0, #CLKCTL_CBCMR]
313 orr r1, r1, #(1 << 16)
314 str r1, [r0, #CLKCTL_CBCDR]
315 /* make sure change is effective */
316 1: ldr r1, [r0, #CLKCTL_CDHIPR]
320 setup_pll PLL2_BASE_ADDR, 400
322 /* Switch peripheral to PLL2 */
323 ldr r0, =CCM_BASE_ADDR
325 orr r1, r1, #(2 << 10)
326 orr r1, r1, #(0 << 16)
327 orr r1, r1, #(1 << 19)
328 str r1, [r0, #CLKCTL_CBCDR]
331 str r1, [r0, #CLKCTL_CBCMR]
333 /*change uart clk parent to pll2*/
334 ldr r1, [r0, #CLKCTL_CSCMR1]
335 and r1, r1, #0xfcffffff
336 orr r1, r1, #0x01000000
337 str r1, [r0, #CLKCTL_CSCMR1]
339 /* make sure change is effective */
340 1: ldr r1, [r0, #CLKCTL_CDHIPR]
344 setup_pll PLL3_BASE_ADDR, 216
346 setup_pll PLL4_BASE_ADDR, 455
348 /* Set the platform clock dividers */
349 ldr r0, =ARM_BASE_ADDR
353 ldr r0, =CCM_BASE_ADDR
355 str r1, [r0, #CLKCTL_CACRR]
357 /* Switch ARM back to PLL 1. */
359 str r1, [r0, #CLKCTL_CCSR]
361 /* make uart div=6 */
362 ldr r1, [r0, #CLKCTL_CSCDR1]
363 and r1, r1, #0xffffffc0
365 str r1, [r0, #CLKCTL_CSCDR1]
367 /* Restore the default values in the Gate registers */
369 str r1, [r0, #CLKCTL_CCGR0]
370 str r1, [r0, #CLKCTL_CCGR1]
371 str r1, [r0, #CLKCTL_CCGR2]
372 str r1, [r0, #CLKCTL_CCGR3]
373 str r1, [r0, #CLKCTL_CCGR4]
374 str r1, [r0, #CLKCTL_CCGR5]
375 str r1, [r0, #CLKCTL_CCGR6]
376 str r1, [r0, #CLKCTL_CCGR7]
379 str r1, [r0, #CLKCTL_CCDR]
381 /* for cko - for ARM div by 8 */
383 add r1, r1, #0x00000F0
384 str r1, [r0, #CLKCTL_CCOSR]
386 #endif /* CONFIG_MX53 */
390 ldr r0, =WDOG1_BASE_ADDR
397 mov r4, #0 /* Fix R4 to 0 */
399 #if defined(CONFIG_SYS_MAIN_PWR_ON)
400 ldr r0, =GPIO1_BASE_ADDR
420 ENDPROC(lowlevel_init)
422 /* Board level setting value */
423 #if defined(CONFIG_MX51_PLL_ERRATA)
424 W_DP_864: .word DP_OP_864
427 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
429 W_DP_800: .word DP_OP_800
433 #if defined(CONFIG_MX51)
434 W_DP_665: .word DP_OP_665
438 W_DP_216: .word DP_OP_216
441 W_DP_400: .word DP_OP_400
444 W_DP_455: .word DP_OP_455