2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <generated/asm-offsets.h>
25 #include <linux/linkage.h>
28 * L2CC Cache setup/invalidation/disable
31 /* explicitly disable L2 cache */
32 mrc 15, 0, r0, c1, c0, 1
34 mcr 15, 0, r0, c1, c0, 1
36 /* reconfigure L2 cache aux control reg */
37 mov r0, #0xC0 /* tag RAM */
38 add r0, r0, #0x4 /* data RAM */
39 orr r0, r0, #1 << 24 /* disable write allocate delay */
40 orr r0, r0, #1 << 23 /* disable write allocate combine */
41 orr r0, r0, #1 << 22 /* disable write allocate */
43 #if defined(CONFIG_MX51)
45 ldr r3, [r1, #ROM_SI_REV]
48 /* disable write combine for TO 2 and lower revs */
49 orrls r0, r0, #1 << 25
52 mcr 15, 1, r0, c9, c0, 2
55 /* AIPS setup - Only setup MPROTx registers.
56 * The PACR default values are good.*/
59 * Set all MPROTx to be non-bufferable, trusted for R/W,
60 * not forced to user-mode.
62 ldr r0, =AIPS1_BASE_ADDR
66 ldr r0, =AIPS2_BASE_ADDR
70 * Clear the on and off peripheral modules Supervisor Protect bit
71 * for SDMA to access them. Did not change the AIPS control registers
72 * (offset 0x20) access type
79 /* VPU and IPU given higher priority (0x4)
80 * IPU accesses with ID=0x1 given highest priority (=0xA)
82 ldr r0, =M4IF_BASE_ADDR
99 .macro setup_pll pll, freq
102 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
104 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
106 ldr r1, W_DP_OP_\freq
107 str r1, [r0, #PLL_DP_OP]
108 str r1, [r0, #PLL_DP_HFS_OP]
110 ldr r1, W_DP_MFD_\freq
111 str r1, [r0, #PLL_DP_MFD]
112 str r1, [r0, #PLL_DP_HFS_MFD]
114 ldr r1, W_DP_MFN_\freq
115 str r1, [r0, #PLL_DP_MFN]
116 str r1, [r0, #PLL_DP_HFS_MFN]
119 str r1, [r0, #PLL_DP_CTL]
120 1: ldr r1, [r0, #PLL_DP_CTL]
125 .macro setup_pll_errata pll, freq
128 str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
130 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
131 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
136 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
137 str r5, [r2, #PLL_DP_HFS_MFN]
140 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
142 2: ldr r1, [r2, #PLL_DP_CONFIG]
146 ldr r1, =100 /* Wait at least 4 us */
151 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
155 ldr r0, =CCM_BASE_ADDR
157 #if defined(CONFIG_MX51)
158 /* Gate of clocks to the peripherals first */
160 str r1, [r0, #CLKCTL_CCGR0]
162 str r1, [r0, #CLKCTL_CCGR1]
163 str r1, [r0, #CLKCTL_CCGR2]
164 str r1, [r0, #CLKCTL_CCGR3]
167 str r1, [r0, #CLKCTL_CCGR4]
169 str r1, [r0, #CLKCTL_CCGR5]
171 str r1, [r0, #CLKCTL_CCGR6]
173 /* Disable IPU and HSC dividers */
175 str r1, [r0, #CLKCTL_CCDR]
177 /* Make sure to switch the DDR away from PLL 1 */
179 str r1, [r0, #CLKCTL_CBCDR]
180 /* make sure divider effective */
181 1: ldr r1, [r0, #CLKCTL_CDHIPR]
186 str r1, [r0, #CLKCTL_CCGR0]
188 str r1, [r0, #CLKCTL_CCGR1]
189 str r1, [r0, #CLKCTL_CCGR2]
190 str r1, [r0, #CLKCTL_CCGR3]
191 str r1, [r0, #CLKCTL_CCGR7]
194 str r1, [r0, #CLKCTL_CCGR4]
196 str r1, [r0, #CLKCTL_CCGR5]
198 str r1, [r0, #CLKCTL_CCGR6]
201 /* Switch ARM to step clock */
203 str r1, [r0, #CLKCTL_CCSR]
205 #if defined(CONFIG_MX51_PLL_ERRATA)
206 setup_pll PLL1_BASE_ADDR, 864
207 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
209 setup_pll PLL1_BASE_ADDR, 800
212 #if defined(CONFIG_MX51)
213 setup_pll PLL3_BASE_ADDR, 665
215 /* Switch peripheral to PLL 3 */
216 ldr r0, =CCM_BASE_ADDR
218 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
219 str r1, [r0, #CLKCTL_CBCMR]
221 str r1, [r0, #CLKCTL_CBCDR]
222 setup_pll PLL2_BASE_ADDR, 665
224 /* Switch peripheral to PLL2 */
225 ldr r0, =CCM_BASE_ADDR
227 str r1, [r0, #CLKCTL_CBCDR]
229 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
230 str r1, [r0, #CLKCTL_CBCMR]
232 setup_pll PLL3_BASE_ADDR, 216
234 /* Set the platform clock dividers */
235 ldr r0, =ARM_BASE_ADDR
239 ldr r0, =CCM_BASE_ADDR
241 #if defined(CONFIG_MX51)
242 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
244 ldr r3, [r1, #ROM_SI_REV]
251 str r1, [r0, #CLKCTL_CACRR]
253 /* Switch ARM back to PLL 1 */
255 str r1, [r0, #CLKCTL_CCSR]
257 #if defined(CONFIG_MX51)
259 /* Use lp_apm (24MHz) source for perclk */
261 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
262 str r1, [r0, #CLKCTL_CBCMR]
263 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
264 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
265 str r1, [r0, #CLKCTL_CBCDR]
268 /* Restore the default values in the Gate registers */
270 str r1, [r0, #CLKCTL_CCGR0]
271 str r1, [r0, #CLKCTL_CCGR1]
272 str r1, [r0, #CLKCTL_CCGR2]
273 str r1, [r0, #CLKCTL_CCGR3]
274 str r1, [r0, #CLKCTL_CCGR4]
275 str r1, [r0, #CLKCTL_CCGR5]
276 str r1, [r0, #CLKCTL_CCGR6]
277 #if defined(CONFIG_MX53)
278 str r1, [r0, #CLKCTL_CCGR7]
281 #if defined(CONFIG_MX51)
282 /* Use PLL 2 for UART's, get 66.5MHz from it */
284 str r1, [r0, #CLKCTL_CSCMR1]
286 str r1, [r0, #CLKCTL_CSCDR1]
287 #elif defined(CONFIG_MX53)
288 /* Switch peripheral to PLL2 */
289 ldr r0, =CCM_BASE_ADDR
294 str r1, [r0, #CLKCTL_CBCDR]
297 str r1, [r0, #CLKCTL_CBCMR]
298 /* Change uart clk parent to pll2*/
299 ldr r1, [r0, #CLKCTL_CSCMR1]
300 and r1, r1, #0xfcffffff
301 orr r1, r1, #0x01000000
302 str r1, [r0, #CLKCTL_CSCMR1]
303 ldr r1, [r0, #CLKCTL_CSCDR1]
304 and r1, r1, #0xffffffc0
306 str r1, [r0, #CLKCTL_CSCDR1]
308 /* make sure divider effective */
309 1: ldr r1, [r0, #CLKCTL_CDHIPR]
314 str r1, [r0, #CLKCTL_CCDR]
316 /* for cko - for ARM div by 8 */
318 add r1, r1, #0x00000F0
319 str r1, [r0, #CLKCTL_CCOSR]
323 ldr r0, =WDOG1_BASE_ADDR
328 .section ".text.init", "x"
331 #if defined(CONFIG_MX51)
332 ldr r0, =GPIO1_BASE_ADDR
349 /* r12 saved upper lr*/
351 ENDPROC(lowlevel_init)
353 /* Board level setting value */
354 W_DP_OP_864: .word DP_OP_864
355 W_DP_MFD_864: .word DP_MFD_864
356 W_DP_MFN_864: .word DP_MFN_864
357 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
358 W_DP_OP_800: .word DP_OP_800
359 W_DP_MFD_800: .word DP_MFD_800
360 W_DP_MFN_800: .word DP_MFN_800
361 W_DP_OP_665: .word DP_OP_665
362 W_DP_MFD_665: .word DP_MFD_665
363 W_DP_MFN_665: .word DP_MFN_665
364 W_DP_OP_216: .word DP_OP_216
365 W_DP_MFD_216: .word DP_MFD_216
366 W_DP_MFN_216: .word DP_MFN_216