2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <generated/asm-offsets.h>
25 #include <linux/linkage.h>
27 .section ".text.init", "x"
30 * L2CC Cache setup/invalidation/disable
33 /* explicitly disable L2 cache */
34 mrc 15, 0, r0, c1, c0, 1
36 mcr 15, 0, r0, c1, c0, 1
38 /* reconfigure L2 cache aux control reg */
39 ldr r0, =0xC0 | /* tag RAM */ \
40 0x4 | /* data RAM */ \
41 1 << 24 | /* disable write allocate delay */ \
42 1 << 23 | /* disable write allocate combine */ \
43 1 << 22 /* disable write allocate */
45 #if defined(CONFIG_MX51)
46 ldr r3, [r4, #ROM_SI_REV]
49 /* disable write combine for TO 2 and lower revs */
50 orrls r0, r0, #1 << 25
53 mcr 15, 1, r0, c9, c0, 2
56 /* AIPS setup - Only setup MPROTx registers.
57 * The PACR default values are good.*/
60 * Set all MPROTx to be non-bufferable, trusted for R/W,
61 * not forced to user-mode.
63 ldr r0, =AIPS1_BASE_ADDR
67 ldr r0, =AIPS2_BASE_ADDR
71 * Clear the on and off peripheral modules Supervisor Protect bit
72 * for SDMA to access them. Did not change the AIPS control registers
73 * (offset 0x20) access type
80 /* VPU and IPU given higher priority (0x4)
81 * IPU accesses with ID=0x1 given highest priority (=0xA)
83 ldr r0, =M4IF_BASE_ADDR
99 .macro setup_pll pll, freq
111 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
113 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
115 ldr r1, [r2, #W_DP_OP]
116 str r1, [r0, #PLL_DP_OP]
117 str r1, [r0, #PLL_DP_HFS_OP]
119 ldr r1, [r2, #W_DP_MFD]
120 str r1, [r0, #PLL_DP_MFD]
121 str r1, [r0, #PLL_DP_HFS_MFD]
123 ldr r1, [r2, #W_DP_MFN]
124 str r1, [r0, #PLL_DP_MFN]
125 str r1, [r0, #PLL_DP_HFS_MFN]
128 str r1, [r0, #PLL_DP_CTL]
129 1: ldr r1, [r0, #PLL_DP_CTL]
133 /* r10 saved upper lr */
136 .macro setup_pll_errata pll, freq
138 str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
140 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
141 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
146 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
147 str r5, [r2, #PLL_DP_HFS_MFN]
150 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
152 2: ldr r1, [r2, #PLL_DP_CONFIG]
156 ldr r1, =100 /* Wait at least 4 us */
161 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
165 #if defined (CONFIG_MX51)
166 ldr r0, =CCM_BASE_ADDR
168 /* Gate of clocks to the peripherals first */
170 str r1, [r0, #CLKCTL_CCGR0]
171 str r4, [r0, #CLKCTL_CCGR1]
172 str r4, [r0, #CLKCTL_CCGR2]
173 str r4, [r0, #CLKCTL_CCGR3]
176 str r1, [r0, #CLKCTL_CCGR4]
178 str r1, [r0, #CLKCTL_CCGR5]
180 str r1, [r0, #CLKCTL_CCGR6]
182 /* Disable IPU and HSC dividers */
184 str r1, [r0, #CLKCTL_CCDR]
186 /* Make sure to switch the DDR away from PLL 1 */
188 str r1, [r0, #CLKCTL_CBCDR]
189 /* make sure divider effective */
190 1: ldr r1, [r0, #CLKCTL_CDHIPR]
194 /* Switch ARM to step clock */
196 str r1, [r0, #CLKCTL_CCSR]
198 #if defined(CONFIG_MX51_PLL_ERRATA)
199 setup_pll PLL1_BASE_ADDR, 864
200 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
202 setup_pll PLL1_BASE_ADDR, 800
205 setup_pll PLL3_BASE_ADDR, 665
207 /* Switch peripheral to PLL 3 */
208 ldr r0, =CCM_BASE_ADDR
209 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
210 str r1, [r0, #CLKCTL_CBCMR]
212 str r1, [r0, #CLKCTL_CBCDR]
213 setup_pll PLL2_BASE_ADDR, 665
215 /* Switch peripheral to PLL2 */
216 ldr r0, =CCM_BASE_ADDR
218 str r1, [r0, #CLKCTL_CBCDR]
219 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
220 str r1, [r0, #CLKCTL_CBCMR]
222 setup_pll PLL3_BASE_ADDR, 216
224 /* Set the platform clock dividers */
225 ldr r0, =ARM_BASE_ADDR
229 ldr r0, =CCM_BASE_ADDR
231 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
232 ldr r3, [r4, #ROM_SI_REV]
237 str r1, [r0, #CLKCTL_CACRR]
239 /* Switch ARM back to PLL 1 */
240 str r4, [r0, #CLKCTL_CCSR]
243 /* Use lp_apm (24MHz) source for perclk */
244 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
245 str r1, [r0, #CLKCTL_CBCMR]
246 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
247 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
248 str r1, [r0, #CLKCTL_CBCDR]
250 /* Restore the default values in the Gate registers */
252 str r1, [r0, #CLKCTL_CCGR0]
253 str r1, [r0, #CLKCTL_CCGR1]
254 str r1, [r0, #CLKCTL_CCGR2]
255 str r1, [r0, #CLKCTL_CCGR3]
256 str r1, [r0, #CLKCTL_CCGR4]
257 str r1, [r0, #CLKCTL_CCGR5]
258 str r1, [r0, #CLKCTL_CCGR6]
260 /* Use PLL 2 for UART's, get 66.5MHz from it */
262 str r1, [r0, #CLKCTL_CSCMR1]
264 str r1, [r0, #CLKCTL_CSCDR1]
265 /* make sure divider effective */
266 1: ldr r1, [r0, #CLKCTL_CDHIPR]
270 str r4, [r0, #CLKCTL_CCDR]
272 /* for cko - for ARM div by 8 */
274 add r1, r1, #0x00000F0
275 str r1, [r0, #CLKCTL_CCOSR]
276 #else /* CONFIG_MX53 */
277 ldr r0, =CCM_BASE_ADDR
279 /* Gate of clocks to the peripherals first */
281 str r1, [r0, #CLKCTL_CCGR0]
282 str r4, [r0, #CLKCTL_CCGR1]
283 str r4, [r0, #CLKCTL_CCGR2]
284 str r4, [r0, #CLKCTL_CCGR3]
285 str r4, [r0, #CLKCTL_CCGR7]
287 str r1, [r0, #CLKCTL_CCGR4]
289 str r1, [r0, #CLKCTL_CCGR5]
291 str r1, [r0, #CLKCTL_CCGR6]
293 /* Switch ARM to step clock */
295 str r1, [r0, #CLKCTL_CCSR]
297 setup_pll PLL1_BASE_ADDR, 800
299 setup_pll PLL3_BASE_ADDR, 216
301 /* Set the platform clock dividers */
302 ldr r0, =ARM_BASE_ADDR
306 ldr r0, =CCM_BASE_ADDR
309 str r1, [r0, #CLKCTL_CACRR]
311 /* Switch ARM back to PLL 1 */
312 str r4, [r0, #CLKCTL_CCSR]
314 /* Restore the default values in the Gate registers */
316 str r1, [r0, #CLKCTL_CCGR0]
317 str r1, [r0, #CLKCTL_CCGR1]
318 str r1, [r0, #CLKCTL_CCGR2]
319 str r1, [r0, #CLKCTL_CCGR3]
320 str r1, [r0, #CLKCTL_CCGR4]
321 str r1, [r0, #CLKCTL_CCGR5]
322 str r1, [r0, #CLKCTL_CCGR6]
323 str r1, [r0, #CLKCTL_CCGR7]
325 /* Switch peripheral to PLL2 */
326 ldr r0, =CCM_BASE_ADDR
330 str r1, [r0, #CLKCTL_CBCDR]
333 str r1, [r0, #CLKCTL_CBCMR]
334 /* Change uart clk parent to pll2*/
335 ldr r1, [r0, #CLKCTL_CSCMR1]
336 and r1, r1, #0xfcffffff
337 orr r1, r1, #0x01000000
338 str r1, [r0, #CLKCTL_CSCMR1]
339 ldr r1, [r0, #CLKCTL_CSCDR1]
340 and r1, r1, #0xffffffc0
342 str r1, [r0, #CLKCTL_CSCDR1]
344 /* make sure divider effective */
345 1: ldr r1, [r0, #CLKCTL_CDHIPR]
349 str r4, [r0, #CLKCTL_CCDR]
351 /* for cko - for ARM div by 8 */
353 add r1, r1, #0x00000F0
354 str r1, [r0, #CLKCTL_CCOSR]
355 #endif /* CONFIG_MX53 */
359 ldr r0, =WDOG1_BASE_ADDR
366 mov r4, #0 /* Fix R4 to 0 */
368 #if defined(CONFIG_MX51)
369 ldr r0, =GPIO1_BASE_ADDR
387 ENDPROC(lowlevel_init)
389 /* Board level setting value */
390 #if defined(CONFIG_MX51_PLL_ERRATA)
391 W_DP_864: .word DP_OP_864
394 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
396 W_DP_800: .word DP_OP_800
400 #if defined(CONFIG_MX51)
401 W_DP_665: .word DP_OP_665
405 W_DP_216: .word DP_OP_216