3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/errno.h>
32 #ifdef CONFIG_FSL_ESDHC
33 #include <fsl_esdhc.h>
36 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
37 #error "CPU_TYPE not defined"
43 int system_rev = 0x51000;
45 int system_rev = 0x53000;
47 int reg = __raw_readl(ROM_SI_REV);
49 #if defined(CONFIG_MX51)
52 system_rev |= CHIP_REV_1_1;
55 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
56 system_rev |= CHIP_REV_2_5;
58 system_rev |= CHIP_REV_2_0;
61 system_rev |= CHIP_REV_3_0;
64 system_rev |= CHIP_REV_1_0;
69 system_rev |= CHIP_REV_1_0;
76 static char *get_reset_cause(void)
79 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
81 cause = readl(&src_regs->srsr);
82 writel(cause, &src_regs->srsr);
100 return "unknown reset";
104 #if defined(CONFIG_DISPLAY_CPUINFO)
105 int print_cpuinfo(void)
109 cpurev = get_cpu_rev();
110 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
111 (cpurev & 0xFF000) >> 12,
112 (cpurev & 0x000F0) >> 4,
113 (cpurev & 0x0000F) >> 0,
114 mxc_get_clock(MXC_ARM_CLK) / 1000000);
115 printf("Reset cause: %s\n", get_reset_cause());
121 * Initializes on-chip ethernet controllers.
122 * to override, implement board_eth_init()
124 #if defined(CONFIG_FEC_MXC)
125 extern int fecmxc_initialize(bd_t *bis);
128 int cpu_eth_init(bd_t *bis)
132 #if defined(CONFIG_FEC_MXC)
133 rc = fecmxc_initialize(bis);
139 #if defined(CONFIG_FEC_MXC)
140 void imx_get_mac_from_fuse(unsigned char *mac)
143 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
144 struct fuse_bank *bank = &iim->bank[1];
145 struct fuse_bank1_regs *fuse =
146 (struct fuse_bank1_regs *)bank->fuse_regs;
148 for (i = 0; i < 6; i++)
149 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
154 * Initializes on-chip MMC controllers.
155 * to override, implement board_mmc_init()
157 int cpu_mmc_init(bd_t *bis)
159 #ifdef CONFIG_FSL_ESDHC
160 return fsl_esdhc_mmc_init(bis);
166 void set_chipselect_size(int const cs_size)
169 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
170 reg = readl(&iomuxc_regs->gpr1);
174 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
177 case CS0_64M_CS1_64M:
178 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
181 case CS0_64M_CS1_32M_CS2_32M:
182 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
185 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
186 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
190 printf("Unknown chip select size: %d\n", cs_size);
194 writel(reg, &iomuxc_regs->gpr1);
197 void reset_cpu(ulong addr)
199 __raw_writew(4, WDOG1_BASE_ADDR);