2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
30 reg = __raw_readl(&imx_ccm->CCGR2);
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
39 #ifdef CONFIG_NAND_MXS
40 void setup_gpmi_io_clk(u32 cfg)
42 /* Disable clocks per ERR007177 from MX6 errata */
43 clrbits_le32(&imx_ccm->CCGR4,
44 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
45 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
46 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
48 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
50 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
52 clrsetbits_le32(&imx_ccm->cs2cdr,
53 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
54 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
55 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
58 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
59 setbits_le32(&imx_ccm->CCGR4,
60 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
62 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
63 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
64 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
68 void enable_usboh3_clk(unsigned char enable)
72 reg = __raw_readl(&imx_ccm->CCGR6);
74 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
76 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
77 __raw_writel(reg, &imx_ccm->CCGR6);
81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
82 void enable_enet_clk(unsigned char enable)
84 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
87 setbits_le32(&imx_ccm->CCGR1, mask);
89 clrbits_le32(&imx_ccm->CCGR1, mask);
93 #ifdef CONFIG_MXC_UART
94 void enable_uart_clk(unsigned char enable)
96 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
99 setbits_le32(&imx_ccm->CCGR5, mask);
101 clrbits_le32(&imx_ccm->CCGR5, mask);
106 /* spi_num can be from 0 - 4 */
107 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
114 mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
116 setbits_le32(&imx_ccm->CCGR1, mask);
118 clrbits_le32(&imx_ccm->CCGR1, mask);
125 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
132 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
134 setbits_le32(&imx_ccm->CCGR6, mask);
136 clrbits_le32(&imx_ccm->CCGR6, mask);
142 #ifdef CONFIG_SYS_I2C_MXC
143 /* i2c_num can be from 0 - 2 */
144 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
152 mask = MXC_CCM_CCGR_CG_MASK
153 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
154 reg = __raw_readl(&imx_ccm->CCGR2);
159 __raw_writel(reg, &imx_ccm->CCGR2);
164 /* spi_num can be from 0 - SPI_MAX_NUM */
165 int enable_spi_clk(unsigned char enable, unsigned spi_num)
170 if (spi_num > SPI_MAX_NUM)
173 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
174 reg = __raw_readl(&imx_ccm->CCGR1);
179 __raw_writel(reg, &imx_ccm->CCGR1);
182 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
188 div = __raw_readl(&imx_ccm->analog_pll_sys);
189 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
191 return (infreq * div) >> 1;
193 div = __raw_readl(&imx_ccm->analog_pll_528);
194 div &= BM_ANADIG_PLL_528_DIV_SELECT;
196 return infreq * (20 + (div << 1));
198 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
199 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
201 return infreq * (20 + (div << 1));
203 div = __raw_readl(&imx_ccm->analog_pll_enet);
204 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
206 return 25000000 * (div + (div >> 1) + 1);
212 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
220 /* No PFD3 on PPL2 */
223 div = __raw_readl(&imx_ccm->analog_pfd_528);
224 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
227 div = __raw_readl(&imx_ccm->analog_pfd_480);
228 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
231 /* No PFD on other PLL */
235 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
236 ANATOP_PFD_FRAC_SHIFT(pfd_num));
239 static u32 get_mcu_main_clk(void)
243 reg = __raw_readl(&imx_ccm->cacrr);
244 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
245 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
246 freq = decode_pll(PLL_SYS, MXC_HCLK);
248 return freq / (reg + 1);
251 u32 get_periph_clk(void)
255 reg = __raw_readl(&imx_ccm->cbcdr);
256 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
257 reg = __raw_readl(&imx_ccm->cbcmr);
258 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
259 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
263 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
273 reg = __raw_readl(&imx_ccm->cbcmr);
274 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
275 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
279 freq = decode_pll(PLL_BUS, MXC_HCLK);
282 freq = mxc_get_pll_pfd(PLL_BUS, 2);
285 freq = mxc_get_pll_pfd(PLL_BUS, 0);
288 /* static / 2 divider */
289 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
299 static u32 get_ipg_clk(void)
303 reg = __raw_readl(&imx_ccm->cbcdr);
304 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
305 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
307 return get_ahb_clk() / (ipg_podf + 1);
310 static u32 get_ipg_per_clk(void)
312 u32 reg, perclk_podf;
314 reg = __raw_readl(&imx_ccm->cscmr1);
315 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
316 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
317 return MXC_HCLK; /* OSC 24Mhz */
319 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
321 return get_ipg_clk() / (perclk_podf + 1);
324 static u32 get_uart_clk(void)
327 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
328 reg = __raw_readl(&imx_ccm->cscdr1);
329 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
330 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
333 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
334 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
336 return freq / (uart_podf + 1);
339 static u32 get_cspi_clk(void)
343 reg = __raw_readl(&imx_ccm->cscdr2);
344 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
345 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
347 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
350 static u32 get_axi_clk(void)
352 u32 root_freq, axi_podf;
353 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
355 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
356 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
358 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
359 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
360 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
362 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
364 root_freq = get_periph_clk();
366 return root_freq / (axi_podf + 1);
369 static u32 get_emi_slow_clk(void)
371 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
373 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
374 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
375 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
376 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
377 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
379 switch (emi_clk_sel) {
381 root_freq = get_axi_clk();
384 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
387 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
390 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
394 return root_freq / (emi_slow_podf + 1);
397 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
398 static u32 get_mmdc_ch0_clk(void)
400 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
401 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
404 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
405 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
407 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
408 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
410 freq = decode_pll(PLL_BUS, MXC_HCLK);
413 freq = mxc_get_pll_pfd(PLL_BUS, 2);
416 freq = mxc_get_pll_pfd(PLL_BUS, 0);
419 /* static / 2 divider */
420 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
423 return freq / (podf + 1);
427 static u32 get_mmdc_ch0_clk(void)
429 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
430 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
431 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
433 return get_periph_clk() / (mmdc_ch0_podf + 1);
438 /* qspi_num can be from 0 - 1 */
439 void enable_qspi_clk(int qspi_num)
442 /* Enable QuadSPI clock */
445 /* disable the clock gate */
446 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
448 /* set 50M : (50 = 396 / 2 / 4) */
449 reg = readl(&imx_ccm->cscmr1);
450 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
451 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
452 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
453 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
454 writel(reg, &imx_ccm->cscmr1);
456 /* enable the clock gate */
457 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
461 * disable the clock gate
462 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
463 * disable both of them.
465 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
466 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
468 /* set 50M : (50 = 396 / 2 / 4) */
469 reg = readl(&imx_ccm->cs2cdr);
470 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
471 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
472 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
473 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
474 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
475 writel(reg, &imx_ccm->cs2cdr);
477 /*enable the clock gate*/
478 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
479 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
487 #ifdef CONFIG_FEC_MXC
488 int enable_fec_anatop_clock(enum enet_freq freq)
491 s32 timeout = 100000;
493 struct anatop_regs __iomem *anatop =
494 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
496 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
499 reg = readl(&anatop->pll_enet);
500 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
503 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
504 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
505 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
506 writel(reg, &anatop->pll_enet);
508 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
515 /* Enable FEC clock */
516 reg |= BM_ANADIG_PLL_ENET_ENABLE;
517 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
518 writel(reg, &anatop->pll_enet);
522 * Set enet ahb clock to 200MHz
523 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
525 reg = readl(&imx_ccm->chsccdr);
526 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
527 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
528 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
530 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
532 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
533 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
534 writel(reg, &imx_ccm->chsccdr);
536 /* Enable enet system clock */
537 reg = readl(&imx_ccm->CCGR3);
538 reg |= MXC_CCM_CCGR3_ENET_MASK;
539 writel(reg, &imx_ccm->CCGR3);
545 static u32 get_usdhc_clk(u32 port)
547 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
548 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
549 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
553 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
554 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
555 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
559 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
560 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
561 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
565 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
566 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
567 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
571 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
572 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
573 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
581 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
583 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
585 return root_freq / (usdhc_podf + 1);
588 u32 imx_get_uartclk(void)
590 return get_uart_clk();
593 u32 imx_get_fecclk(void)
595 return mxc_get_clock(MXC_IPG_CLK);
598 static int enable_enet_pll(uint32_t en)
600 struct mxc_ccm_reg *const imx_ccm
601 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
602 s32 timeout = 100000;
606 reg = readl(&imx_ccm->analog_pll_enet);
607 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
608 writel(reg, &imx_ccm->analog_pll_enet);
609 reg |= BM_ANADIG_PLL_SYS_ENABLE;
611 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
616 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
617 writel(reg, &imx_ccm->analog_pll_enet);
619 writel(reg, &imx_ccm->analog_pll_enet);
624 static void ungate_sata_clock(void)
626 struct mxc_ccm_reg *const imx_ccm =
627 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
629 /* Enable SATA clock. */
630 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
634 static void ungate_pcie_clock(void)
636 struct mxc_ccm_reg *const imx_ccm =
637 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
639 /* Enable PCIe clock. */
640 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
644 int enable_sata_clock(void)
647 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
650 void disable_sata_clock(void)
652 struct mxc_ccm_reg *const imx_ccm =
653 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
655 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
659 int enable_pcie_clock(void)
661 struct anatop_regs *anatop_regs =
662 (struct anatop_regs *)ANATOP_BASE_ADDR;
663 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
669 * The register ANATOP_MISC1 is not documented in the Freescale
670 * MX6RM. The register that is mapped in the ANATOP space and
671 * marked as ANATOP_MISC1 is actually documented in the PMU section
672 * of the datasheet as PMU_MISC1.
674 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
675 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
676 * for PCI express link that is clocked from the i.MX6.
678 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
679 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
680 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
681 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
682 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
684 if (is_cpu_type(MXC_CPU_MX6SX))
685 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
687 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
689 clrsetbits_le32(&anatop_regs->ana_misc1,
690 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
691 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
692 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
694 /* PCIe reference clock sourced from AXI. */
695 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
697 /* Party time! Ungate the clock to the PCIe. */
703 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
704 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
707 #ifdef CONFIG_SECURE_BOOT
708 void hab_caam_clock_enable(unsigned char enable)
712 /* CG4 ~ CG6, CAAM clocks */
713 reg = __raw_readl(&imx_ccm->CCGR0);
715 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
716 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
717 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
719 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
720 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
721 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
722 __raw_writel(reg, &imx_ccm->CCGR0);
725 reg = __raw_readl(&imx_ccm->CCGR6);
727 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
729 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
730 __raw_writel(reg, &imx_ccm->CCGR6);
734 static void enable_pll3(void)
736 struct anatop_regs __iomem *anatop =
737 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
739 /* make sure pll3 is enabled */
740 if ((readl(&anatop->usb1_pll_480_ctrl) &
741 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
742 /* enable pll's power */
743 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
744 &anatop->usb1_pll_480_ctrl_set);
745 writel(0x80, &anatop->ana_misc2_clr);
746 /* wait for pll lock */
747 while ((readl(&anatop->usb1_pll_480_ctrl) &
748 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
751 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
752 &anatop->usb1_pll_480_ctrl_clr);
753 /* enable pll output */
754 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
755 &anatop->usb1_pll_480_ctrl_set);
759 void enable_thermal_clk(void)
764 unsigned int mxc_get_clock(enum mxc_clock clk)
768 return get_mcu_main_clk();
770 return get_periph_clk();
772 return get_ahb_clk();
774 return get_ipg_clk();
777 return get_ipg_per_clk();
779 return get_uart_clk();
781 return get_cspi_clk();
783 return get_axi_clk();
784 case MXC_EMI_SLOW_CLK:
785 return get_emi_slow_clk();
787 return get_mmdc_ch0_clk();
789 return get_usdhc_clk(0);
791 return get_usdhc_clk(1);
793 return get_usdhc_clk(2);
795 return get_usdhc_clk(3);
797 return get_ahb_clk();
799 printf("Unsupported MXC CLK: %d\n", clk);
807 * Dump some core clockes.
809 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
812 freq = decode_pll(PLL_SYS, MXC_HCLK);
813 printf("PLL_SYS %8d MHz\n", freq / 1000000);
814 freq = decode_pll(PLL_BUS, MXC_HCLK);
815 printf("PLL_BUS %8d MHz\n", freq / 1000000);
816 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
817 printf("PLL_OTG %8d MHz\n", freq / 1000000);
818 freq = decode_pll(PLL_ENET, MXC_HCLK);
819 printf("PLL_NET %8d MHz\n", freq / 1000000);
822 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
823 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
824 #ifdef CONFIG_MXC_SPI
825 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
827 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
828 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
829 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
830 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
831 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
832 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
833 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
834 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
835 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
841 void enable_ipu_clock(void)
843 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
845 reg = readl(&mxc_ccm->CCGR3);
846 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
847 writel(reg, &mxc_ccm->CCGR3);
850 /***************************************************/
853 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,