2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
30 reg = __raw_readl(&imx_ccm->CCGR2);
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
39 #ifdef CONFIG_NAND_MXS
40 void setup_gpmi_io_clk(u32 cfg)
42 /* Disable clocks per ERR007177 from MX6 errata */
43 clrbits_le32(&imx_ccm->CCGR4,
44 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
45 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
46 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
48 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
50 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
52 clrsetbits_le32(&imx_ccm->cs2cdr,
53 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
54 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
55 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
58 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
59 setbits_le32(&imx_ccm->CCGR4,
60 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
62 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
63 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
64 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
68 void enable_usboh3_clk(unsigned char enable)
72 reg = __raw_readl(&imx_ccm->CCGR6);
74 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
76 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
77 __raw_writel(reg, &imx_ccm->CCGR6);
81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
82 void enable_enet_clk(unsigned char enable)
84 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
87 setbits_le32(&imx_ccm->CCGR1, mask);
89 clrbits_le32(&imx_ccm->CCGR1, mask);
93 #ifdef CONFIG_MXC_UART
94 void enable_uart_clk(unsigned char enable)
96 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
99 setbits_le32(&imx_ccm->CCGR5, mask);
101 clrbits_le32(&imx_ccm->CCGR5, mask);
106 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
113 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
115 setbits_le32(&imx_ccm->CCGR6, mask);
117 clrbits_le32(&imx_ccm->CCGR6, mask);
123 #ifdef CONFIG_SYS_I2C_MXC
124 /* i2c_num can be from 0 - 3 */
125 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
133 mask = MXC_CCM_CCGR_CG_MASK
134 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
136 reg = __raw_readl(&imx_ccm->CCGR2);
141 __raw_writel(reg, &imx_ccm->CCGR2);
143 mask = MXC_CCM_CCGR_CG_MASK
144 << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
145 reg = __raw_readl(&imx_ccm->CCGR1);
150 __raw_writel(reg, &imx_ccm->CCGR1);
156 /* spi_num can be from 0 - SPI_MAX_NUM */
157 int enable_spi_clk(unsigned char enable, unsigned spi_num)
162 if (spi_num > SPI_MAX_NUM)
165 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
166 reg = __raw_readl(&imx_ccm->CCGR1);
171 __raw_writel(reg, &imx_ccm->CCGR1);
174 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
180 div = __raw_readl(&imx_ccm->analog_pll_sys);
181 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
183 return (infreq * div) >> 1;
185 div = __raw_readl(&imx_ccm->analog_pll_528);
186 div &= BM_ANADIG_PLL_528_DIV_SELECT;
188 return infreq * (20 + (div << 1));
190 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
191 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
193 return infreq * (20 + (div << 1));
195 div = __raw_readl(&imx_ccm->analog_pll_enet);
196 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
198 return 25000000 * (div + (div >> 1) + 1);
204 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
212 /* No PFD3 on PPL2 */
215 div = __raw_readl(&imx_ccm->analog_pfd_528);
216 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
219 div = __raw_readl(&imx_ccm->analog_pfd_480);
220 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
223 /* No PFD on other PLL */
227 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
228 ANATOP_PFD_FRAC_SHIFT(pfd_num));
231 static u32 get_mcu_main_clk(void)
235 reg = __raw_readl(&imx_ccm->cacrr);
236 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
237 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
238 freq = decode_pll(PLL_SYS, MXC_HCLK);
240 return freq / (reg + 1);
243 u32 get_periph_clk(void)
247 reg = __raw_readl(&imx_ccm->cbcdr);
248 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
249 reg = __raw_readl(&imx_ccm->cbcmr);
250 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
251 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
255 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
265 reg = __raw_readl(&imx_ccm->cbcmr);
266 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
267 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
271 freq = decode_pll(PLL_BUS, MXC_HCLK);
274 freq = mxc_get_pll_pfd(PLL_BUS, 2);
277 freq = mxc_get_pll_pfd(PLL_BUS, 0);
280 /* static / 2 divider */
281 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
291 static u32 get_ipg_clk(void)
295 reg = __raw_readl(&imx_ccm->cbcdr);
296 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
297 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
299 return get_ahb_clk() / (ipg_podf + 1);
302 static u32 get_ipg_per_clk(void)
304 u32 reg, perclk_podf;
306 reg = __raw_readl(&imx_ccm->cscmr1);
307 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
308 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
309 return MXC_HCLK; /* OSC 24Mhz */
311 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
313 return get_ipg_clk() / (perclk_podf + 1);
316 static u32 get_uart_clk(void)
319 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
320 reg = __raw_readl(&imx_ccm->cscdr1);
321 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
322 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
325 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
326 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
328 return freq / (uart_podf + 1);
331 static u32 get_cspi_clk(void)
335 reg = __raw_readl(&imx_ccm->cscdr2);
336 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
337 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
339 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
342 static u32 get_axi_clk(void)
344 u32 root_freq, axi_podf;
345 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
347 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
348 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
350 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
351 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
352 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
354 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
356 root_freq = get_periph_clk();
358 return root_freq / (axi_podf + 1);
361 static u32 get_emi_slow_clk(void)
363 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
365 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
366 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
367 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
368 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
369 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
371 switch (emi_clk_sel) {
373 root_freq = get_axi_clk();
376 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
379 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
382 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
386 return root_freq / (emi_slow_podf + 1);
389 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
390 static u32 get_mmdc_ch0_clk(void)
392 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
393 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
396 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
397 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
399 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
400 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
402 freq = decode_pll(PLL_BUS, MXC_HCLK);
405 freq = mxc_get_pll_pfd(PLL_BUS, 2);
408 freq = mxc_get_pll_pfd(PLL_BUS, 0);
411 /* static / 2 divider */
412 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
415 return freq / (podf + 1);
419 static u32 get_mmdc_ch0_clk(void)
421 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
422 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
423 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
425 return get_periph_clk() / (mmdc_ch0_podf + 1);
430 /* qspi_num can be from 0 - 1 */
431 void enable_qspi_clk(int qspi_num)
434 /* Enable QuadSPI clock */
437 /* disable the clock gate */
438 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
440 /* set 50M : (50 = 396 / 2 / 4) */
441 reg = readl(&imx_ccm->cscmr1);
442 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
443 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
444 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
445 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
446 writel(reg, &imx_ccm->cscmr1);
448 /* enable the clock gate */
449 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
453 * disable the clock gate
454 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
455 * disable both of them.
457 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
458 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
460 /* set 50M : (50 = 396 / 2 / 4) */
461 reg = readl(&imx_ccm->cs2cdr);
462 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
463 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
464 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
465 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
466 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
467 writel(reg, &imx_ccm->cs2cdr);
469 /*enable the clock gate*/
470 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
471 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
479 #ifdef CONFIG_FEC_MXC
480 int enable_fec_anatop_clock(enum enet_freq freq)
483 s32 timeout = 100000;
485 struct anatop_regs __iomem *anatop =
486 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
488 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
491 reg = readl(&anatop->pll_enet);
492 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
495 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
496 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
497 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
498 writel(reg, &anatop->pll_enet);
500 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
507 /* Enable FEC clock */
508 reg |= BM_ANADIG_PLL_ENET_ENABLE;
509 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
510 writel(reg, &anatop->pll_enet);
514 * Set enet ahb clock to 200MHz
515 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
517 reg = readl(&imx_ccm->chsccdr);
518 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
519 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
520 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
522 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
524 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
525 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
526 writel(reg, &imx_ccm->chsccdr);
528 /* Enable enet system clock */
529 reg = readl(&imx_ccm->CCGR3);
530 reg |= MXC_CCM_CCGR3_ENET_MASK;
531 writel(reg, &imx_ccm->CCGR3);
537 static u32 get_usdhc_clk(u32 port)
539 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
540 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
541 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
545 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
546 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
547 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
551 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
552 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
553 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
557 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
558 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
559 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
563 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
564 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
565 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
573 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
575 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
577 return root_freq / (usdhc_podf + 1);
580 u32 imx_get_uartclk(void)
582 return get_uart_clk();
585 u32 imx_get_fecclk(void)
587 return mxc_get_clock(MXC_IPG_CLK);
590 static int enable_enet_pll(uint32_t en)
592 struct mxc_ccm_reg *const imx_ccm
593 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
594 s32 timeout = 100000;
598 reg = readl(&imx_ccm->analog_pll_enet);
599 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
600 writel(reg, &imx_ccm->analog_pll_enet);
601 reg |= BM_ANADIG_PLL_SYS_ENABLE;
603 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
608 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
609 writel(reg, &imx_ccm->analog_pll_enet);
611 writel(reg, &imx_ccm->analog_pll_enet);
616 static void ungate_sata_clock(void)
618 struct mxc_ccm_reg *const imx_ccm =
619 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
621 /* Enable SATA clock. */
622 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
626 static void ungate_pcie_clock(void)
628 struct mxc_ccm_reg *const imx_ccm =
629 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
631 /* Enable PCIe clock. */
632 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
636 int enable_sata_clock(void)
639 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
642 void disable_sata_clock(void)
644 struct mxc_ccm_reg *const imx_ccm =
645 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
647 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
651 int enable_pcie_clock(void)
653 struct anatop_regs *anatop_regs =
654 (struct anatop_regs *)ANATOP_BASE_ADDR;
655 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
661 * The register ANATOP_MISC1 is not documented in the Freescale
662 * MX6RM. The register that is mapped in the ANATOP space and
663 * marked as ANATOP_MISC1 is actually documented in the PMU section
664 * of the datasheet as PMU_MISC1.
666 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
667 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
668 * for PCI express link that is clocked from the i.MX6.
670 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
671 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
672 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
673 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
674 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
676 if (is_cpu_type(MXC_CPU_MX6SX))
677 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
679 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
681 clrsetbits_le32(&anatop_regs->ana_misc1,
682 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
683 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
684 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
686 /* PCIe reference clock sourced from AXI. */
687 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
689 /* Party time! Ungate the clock to the PCIe. */
695 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
696 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
699 #ifdef CONFIG_SECURE_BOOT
700 void hab_caam_clock_enable(unsigned char enable)
704 /* CG4 ~ CG6, CAAM clocks */
705 reg = __raw_readl(&imx_ccm->CCGR0);
707 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
708 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
709 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
711 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
712 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
713 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
714 __raw_writel(reg, &imx_ccm->CCGR0);
717 reg = __raw_readl(&imx_ccm->CCGR6);
719 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
721 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
722 __raw_writel(reg, &imx_ccm->CCGR6);
726 static void enable_pll3(void)
728 struct anatop_regs __iomem *anatop =
729 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
731 /* make sure pll3 is enabled */
732 if ((readl(&anatop->usb1_pll_480_ctrl) &
733 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
734 /* enable pll's power */
735 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
736 &anatop->usb1_pll_480_ctrl_set);
737 writel(0x80, &anatop->ana_misc2_clr);
738 /* wait for pll lock */
739 while ((readl(&anatop->usb1_pll_480_ctrl) &
740 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
743 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
744 &anatop->usb1_pll_480_ctrl_clr);
745 /* enable pll output */
746 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
747 &anatop->usb1_pll_480_ctrl_set);
751 void enable_thermal_clk(void)
756 unsigned int mxc_get_clock(enum mxc_clock clk)
760 return get_mcu_main_clk();
762 return get_periph_clk();
764 return get_ahb_clk();
766 return get_ipg_clk();
769 return get_ipg_per_clk();
771 return get_uart_clk();
773 return get_cspi_clk();
775 return get_axi_clk();
776 case MXC_EMI_SLOW_CLK:
777 return get_emi_slow_clk();
779 return get_mmdc_ch0_clk();
781 return get_usdhc_clk(0);
783 return get_usdhc_clk(1);
785 return get_usdhc_clk(2);
787 return get_usdhc_clk(3);
789 return get_ahb_clk();
791 printf("Unsupported MXC CLK: %d\n", clk);
799 * Dump some core clockes.
801 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
804 freq = decode_pll(PLL_SYS, MXC_HCLK);
805 printf("PLL_SYS %8d MHz\n", freq / 1000000);
806 freq = decode_pll(PLL_BUS, MXC_HCLK);
807 printf("PLL_BUS %8d MHz\n", freq / 1000000);
808 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
809 printf("PLL_OTG %8d MHz\n", freq / 1000000);
810 freq = decode_pll(PLL_ENET, MXC_HCLK);
811 printf("PLL_NET %8d MHz\n", freq / 1000000);
814 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
815 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
816 #ifdef CONFIG_MXC_SPI
817 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
819 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
820 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
821 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
822 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
823 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
824 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
825 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
826 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
827 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
833 void enable_ipu_clock(void)
835 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
837 reg = readl(&mxc_ccm->CCGR3);
838 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
839 writel(reg, &mxc_ccm->CCGR3);
842 /***************************************************/
845 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,