2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
30 reg = __raw_readl(&imx_ccm->CCGR2);
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
39 #ifdef CONFIG_NAND_MXS
40 void setup_gpmi_io_clk(u32 cfg)
42 /* Disable clocks per ERR007177 from MX6 errata */
43 clrbits_le32(&imx_ccm->CCGR4,
44 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
45 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
46 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
48 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
50 #if defined(CONFIG_MX6SX)
51 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
53 clrsetbits_le32(&imx_ccm->cs2cdr,
54 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
55 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
56 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
59 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
61 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
63 clrsetbits_le32(&imx_ccm->cs2cdr,
64 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
65 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
66 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
69 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
71 setbits_le32(&imx_ccm->CCGR4,
72 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
73 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
74 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
76 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
80 void enable_usboh3_clk(unsigned char enable)
84 reg = __raw_readl(&imx_ccm->CCGR6);
86 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
88 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
89 __raw_writel(reg, &imx_ccm->CCGR6);
93 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
94 void enable_enet_clk(unsigned char enable)
98 if (is_cpu_type(MXC_CPU_MX6UL)) {
99 mask = MXC_CCM_CCGR3_ENET_MASK;
100 addr = &imx_ccm->CCGR3;
102 mask = MXC_CCM_CCGR1_ENET_MASK;
103 addr = &imx_ccm->CCGR1;
107 setbits_le32(addr, mask);
109 clrbits_le32(addr, mask);
113 #ifdef CONFIG_MXC_UART
114 void enable_uart_clk(unsigned char enable)
118 if (is_cpu_type(MXC_CPU_MX6UL))
119 mask = MXC_CCM_CCGR5_UART_MASK;
121 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
124 setbits_le32(&imx_ccm->CCGR5, mask);
126 clrbits_le32(&imx_ccm->CCGR5, mask);
131 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
138 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
140 setbits_le32(&imx_ccm->CCGR6, mask);
142 clrbits_le32(&imx_ccm->CCGR6, mask);
148 #ifdef CONFIG_SYS_I2C_MXC
149 /* i2c_num can be from 0 - 3 */
150 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
159 mask = MXC_CCM_CCGR_CG_MASK
160 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
162 reg = __raw_readl(&imx_ccm->CCGR2);
167 __raw_writel(reg, &imx_ccm->CCGR2);
169 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
170 mask = MXC_CCM_CCGR6_I2C4_MASK;
171 addr = &imx_ccm->CCGR6;
173 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
174 addr = &imx_ccm->CCGR1;
176 reg = __raw_readl(addr);
181 __raw_writel(reg, addr);
187 /* spi_num can be from 0 - SPI_MAX_NUM */
188 int enable_spi_clk(unsigned char enable, unsigned spi_num)
193 if (spi_num > SPI_MAX_NUM)
196 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
197 reg = __raw_readl(&imx_ccm->CCGR1);
202 __raw_writel(reg, &imx_ccm->CCGR1);
205 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
211 div = __raw_readl(&imx_ccm->analog_pll_sys);
212 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
214 return (infreq * div) >> 1;
216 div = __raw_readl(&imx_ccm->analog_pll_528);
217 div &= BM_ANADIG_PLL_528_DIV_SELECT;
219 return infreq * (20 + (div << 1));
221 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
222 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
224 return infreq * (20 + (div << 1));
226 div = __raw_readl(&imx_ccm->analog_pll_enet);
227 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
229 return 25000000 * (div + (div >> 1) + 1);
235 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
242 if (!is_cpu_type(MXC_CPU_MX6UL)) {
244 /* No PFD3 on PPL2 */
248 div = __raw_readl(&imx_ccm->analog_pfd_528);
249 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
252 div = __raw_readl(&imx_ccm->analog_pfd_480);
253 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
256 /* No PFD on other PLL */
260 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
261 ANATOP_PFD_FRAC_SHIFT(pfd_num));
264 static u32 get_mcu_main_clk(void)
268 reg = __raw_readl(&imx_ccm->cacrr);
269 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
270 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
271 freq = decode_pll(PLL_SYS, MXC_HCLK);
273 return freq / (reg + 1);
276 u32 get_periph_clk(void)
278 u32 reg, div = 0, freq = 0;
280 reg = __raw_readl(&imx_ccm->cbcdr);
281 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
282 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
283 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
284 reg = __raw_readl(&imx_ccm->cbcmr);
285 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
286 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
290 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
300 reg = __raw_readl(&imx_ccm->cbcmr);
301 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
302 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
306 freq = decode_pll(PLL_BUS, MXC_HCLK);
309 freq = mxc_get_pll_pfd(PLL_BUS, 2);
312 freq = mxc_get_pll_pfd(PLL_BUS, 0);
315 /* static / 2 divider */
316 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
323 return freq / (div + 1);
326 static u32 get_ipg_clk(void)
330 reg = __raw_readl(&imx_ccm->cbcdr);
331 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
332 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
334 return get_ahb_clk() / (ipg_podf + 1);
337 static u32 get_ipg_per_clk(void)
339 u32 reg, perclk_podf;
341 reg = __raw_readl(&imx_ccm->cscmr1);
342 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
343 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
344 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
345 return MXC_HCLK; /* OSC 24Mhz */
348 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
350 return get_ipg_clk() / (perclk_podf + 1);
353 static u32 get_uart_clk(void)
356 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
357 reg = __raw_readl(&imx_ccm->cscdr1);
359 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
360 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
361 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
365 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
366 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
368 return freq / (uart_podf + 1);
371 static u32 get_cspi_clk(void)
375 reg = __raw_readl(&imx_ccm->cscdr2);
376 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
377 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
379 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
380 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
381 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
382 return MXC_HCLK / (cspi_podf + 1);
385 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
388 static u32 get_axi_clk(void)
390 u32 root_freq, axi_podf;
391 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
393 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
394 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
396 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
397 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
398 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
400 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
402 root_freq = get_periph_clk();
404 return root_freq / (axi_podf + 1);
407 static u32 get_emi_slow_clk(void)
409 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
411 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
412 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
413 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
414 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
415 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
417 switch (emi_clk_sel) {
419 root_freq = get_axi_clk();
422 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
425 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
428 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
432 return root_freq / (emi_slow_podf + 1);
435 static u32 get_mmdc_ch0_clk(void)
437 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
438 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
440 u32 freq, podf, per2_clk2_podf;
442 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
443 is_cpu_type(MXC_CPU_MX6SL)) {
444 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
445 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
446 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
447 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
448 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
449 if (is_cpu_type(MXC_CPU_MX6SL)) {
450 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
453 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
455 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
456 freq = decode_pll(PLL_BUS, MXC_HCLK);
458 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
463 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
464 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
466 freq = decode_pll(PLL_BUS, MXC_HCLK);
469 freq = mxc_get_pll_pfd(PLL_BUS, 2);
472 freq = mxc_get_pll_pfd(PLL_BUS, 0);
475 /* static / 2 divider */
476 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
480 return freq / (podf + 1) / (per2_clk2_podf + 1);
482 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
483 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
484 return get_periph_clk() / (podf + 1);
488 #if defined(CONFIG_VIDEO_MXS)
489 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
495 debug("pll5 div = %d, num = %d, denom = %d\n",
496 pll_div, pll_num, pll_denom);
498 /* Power up PLL5 video */
499 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
500 BM_ANADIG_PLL_VIDEO_BYPASS |
501 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
502 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
503 &imx_ccm->analog_pll_video_clr);
505 /* Set div, num and denom */
508 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
509 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
510 &imx_ccm->analog_pll_video_set);
513 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
514 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
515 &imx_ccm->analog_pll_video_set);
518 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
519 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
520 &imx_ccm->analog_pll_video_set);
523 puts("Wrong test_div!\n");
527 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
528 &imx_ccm->analog_pll_video_num);
529 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
530 &imx_ccm->analog_pll_video_denom);
533 start = get_timer(0); /* Get current timestamp */
536 reg = readl(&imx_ccm->analog_pll_video);
537 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
539 writel(BM_ANADIG_PLL_VIDEO_ENABLE,
540 &imx_ccm->analog_pll_video_set);
543 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
545 puts("Lock PLL5 timeout\n");
551 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
553 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
555 void mxs_set_lcdclk(u32 base_addr, u32 freq)
558 u32 hck = MXC_HCLK / 1000;
559 /* DIV_SELECT ranges from 27 to 54 */
563 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
564 u32 pll_div, pll_num, pll_denom, post_div = 1;
566 debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
568 if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
569 debug("This chip not support lcd!\n");
573 if (base_addr == LCDIF1_BASE_ADDR) {
574 reg = readl(&imx_ccm->cscdr2);
575 /* Can't change clocks when clock not from pre-mux */
576 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
580 if (is_cpu_type(MXC_CPU_MX6SX)) {
581 reg = readl(&imx_ccm->cscdr2);
582 /* Can't change clocks when clock not from pre-mux */
583 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
587 temp = freq * max_pred * max_postd;
589 puts("Please decrease freq, too large!\n");
594 * Register: PLL_VIDEO
595 * Bit Field: POST_DIV_SELECT
596 * 00 — Divide by 4.
597 * 01 — Divide by 2.
598 * 10 — Divide by 1.
600 * No need to check post_div(1)
602 for (post_div = 2; post_div <= 4; post_div <<= 1) {
603 if ((temp * post_div) > min) {
610 printf("Fail to set rate to %dkhz", freq);
615 /* Choose the best pred and postd to match freq for lcd */
616 for (i = 1; i <= max_pred; i++) {
617 for (j = 1; j <= max_postd; j++) {
619 if (temp > max || temp < min)
621 if (best == 0 || temp < best) {
630 printf("Fail to set rate to %dKHz", freq);
634 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
636 pll_div = best / hck;
638 pll_num = (best - hck * pll_div) * pll_denom / hck;
642 * (24MHz * (pll_div + --------- ))
644 *freq KHz = --------------------------------
645 * post_div * pred * postd * 1000
648 if (base_addr == LCDIF1_BASE_ADDR) {
649 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
652 /* Select pre-lcd clock to PLL5 and set pre divider */
653 clrsetbits_le32(&imx_ccm->cscdr2,
654 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
655 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
656 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
658 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
660 /* Set the post divider */
661 clrsetbits_le32(&imx_ccm->cbcmr,
662 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
664 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
665 } else if (is_cpu_type(MXC_CPU_MX6SX)) {
666 /* Setting LCDIF2 for i.MX6SX */
667 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
670 /* Select pre-lcd clock to PLL5 and set pre divider */
671 clrsetbits_le32(&imx_ccm->cscdr2,
672 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
673 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
674 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
676 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
678 /* Set the post divider */
679 clrsetbits_le32(&imx_ccm->cscmr1,
680 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
682 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
686 int enable_lcdif_clock(u32 base_addr)
689 u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
691 if (is_cpu_type(MXC_CPU_MX6SX)) {
692 if ((base_addr == LCDIF1_BASE_ADDR) ||
693 (base_addr == LCDIF2_BASE_ADDR)) {
694 puts("Wrong LCD interface!\n");
697 /* Set to pre-mux clock at default */
698 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
699 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
700 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
701 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
702 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
703 MXC_CCM_CCGR3_DISP_AXI_MASK) :
704 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
705 MXC_CCM_CCGR3_DISP_AXI_MASK);
706 } else if (is_cpu_type(MXC_CPU_MX6UL)) {
707 if (base_addr != LCDIF1_BASE_ADDR) {
708 puts("Wrong LCD interface!\n");
711 /* Set to pre-mux clock at default */
712 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
713 lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
718 reg = readl(&imx_ccm->cscdr2);
719 reg &= ~lcdif_clk_sel_mask;
720 writel(reg, &imx_ccm->cscdr2);
722 /* Enable the LCDIF pix clock */
723 reg = readl(&imx_ccm->CCGR3);
724 reg |= lcdif_ccgr3_mask;
725 writel(reg, &imx_ccm->CCGR3);
727 reg = readl(&imx_ccm->CCGR2);
728 reg |= MXC_CCM_CCGR2_LCD_MASK;
729 writel(reg, &imx_ccm->CCGR2);
735 #ifdef CONFIG_FSL_QSPI
736 /* qspi_num can be from 0 - 1 */
737 void enable_qspi_clk(int qspi_num)
740 /* Enable QuadSPI clock */
743 /* disable the clock gate */
744 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
746 /* set 50M : (50 = 396 / 2 / 4) */
747 reg = readl(&imx_ccm->cscmr1);
748 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
749 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
750 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
751 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
752 writel(reg, &imx_ccm->cscmr1);
754 /* enable the clock gate */
755 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
759 * disable the clock gate
760 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
761 * disable both of them.
763 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
764 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
766 /* set 50M : (50 = 396 / 2 / 4) */
767 reg = readl(&imx_ccm->cs2cdr);
768 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
769 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
770 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
771 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
772 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
773 writel(reg, &imx_ccm->cs2cdr);
775 /*enable the clock gate*/
776 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
777 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
785 #ifdef CONFIG_FEC_MXC
786 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
789 s32 timeout = 100000;
791 struct anatop_regs __iomem *anatop =
792 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
794 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
797 reg = readl(&anatop->pll_enet);
800 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
801 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
802 } else if (fec_id == 1) {
803 /* Only i.MX6SX/UL support ENET2 */
804 if (!(is_cpu_type(MXC_CPU_MX6SX) ||
805 is_cpu_type(MXC_CPU_MX6UL)))
807 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
808 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
813 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
814 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
815 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
816 writel(reg, &anatop->pll_enet);
818 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
825 /* Enable FEC clock */
827 reg |= BM_ANADIG_PLL_ENET_ENABLE;
829 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
830 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
831 writel(reg, &anatop->pll_enet);
835 * Set enet ahb clock to 200MHz
836 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
838 reg = readl(&imx_ccm->chsccdr);
839 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
840 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
841 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
843 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
845 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
846 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
847 writel(reg, &imx_ccm->chsccdr);
849 /* Enable enet system clock */
850 reg = readl(&imx_ccm->CCGR3);
851 reg |= MXC_CCM_CCGR3_ENET_MASK;
852 writel(reg, &imx_ccm->CCGR3);
858 static u32 get_usdhc_clk(u32 port)
860 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
861 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
862 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
866 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
867 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
868 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
872 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
873 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
874 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
878 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
879 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
880 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
884 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
885 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
886 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
894 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
896 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
898 return root_freq / (usdhc_podf + 1);
901 u32 imx_get_uartclk(void)
903 return get_uart_clk();
906 u32 imx_get_fecclk(void)
908 return mxc_get_clock(MXC_IPG_CLK);
911 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
912 static int enable_enet_pll(uint32_t en)
914 struct mxc_ccm_reg *const imx_ccm
915 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
916 s32 timeout = 100000;
920 reg = readl(&imx_ccm->analog_pll_enet);
921 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
922 writel(reg, &imx_ccm->analog_pll_enet);
923 reg |= BM_ANADIG_PLL_SYS_ENABLE;
925 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
930 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
931 writel(reg, &imx_ccm->analog_pll_enet);
933 writel(reg, &imx_ccm->analog_pll_enet);
938 #ifdef CONFIG_CMD_SATA
939 static void ungate_sata_clock(void)
941 struct mxc_ccm_reg *const imx_ccm =
942 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
944 /* Enable SATA clock. */
945 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
948 int enable_sata_clock(void)
951 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
954 void disable_sata_clock(void)
956 struct mxc_ccm_reg *const imx_ccm =
957 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
959 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
963 #ifdef CONFIG_PCIE_IMX
964 static void ungate_pcie_clock(void)
966 struct mxc_ccm_reg *const imx_ccm =
967 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
969 /* Enable PCIe clock. */
970 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
973 int enable_pcie_clock(void)
975 struct anatop_regs *anatop_regs =
976 (struct anatop_regs *)ANATOP_BASE_ADDR;
977 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
983 * The register ANATOP_MISC1 is not documented in the Freescale
984 * MX6RM. The register that is mapped in the ANATOP space and
985 * marked as ANATOP_MISC1 is actually documented in the PMU section
986 * of the datasheet as PMU_MISC1.
988 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
989 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
990 * for PCI express link that is clocked from the i.MX6.
992 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
993 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
994 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
995 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
996 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
998 if (is_cpu_type(MXC_CPU_MX6SX))
999 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1001 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1003 clrsetbits_le32(&anatop_regs->ana_misc1,
1004 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1005 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1006 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1008 /* PCIe reference clock sourced from AXI. */
1009 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1011 /* Party time! Ungate the clock to the PCIe. */
1012 #ifdef CONFIG_CMD_SATA
1013 ungate_sata_clock();
1015 ungate_pcie_clock();
1017 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1018 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1022 #ifdef CONFIG_SECURE_BOOT
1023 void hab_caam_clock_enable(unsigned char enable)
1027 /* CG4 ~ CG6, CAAM clocks */
1028 reg = __raw_readl(&imx_ccm->CCGR0);
1030 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1031 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1032 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1034 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1035 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1036 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1037 __raw_writel(reg, &imx_ccm->CCGR0);
1040 reg = __raw_readl(&imx_ccm->CCGR6);
1042 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1044 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1045 __raw_writel(reg, &imx_ccm->CCGR6);
1049 static void enable_pll3(void)
1051 struct anatop_regs __iomem *anatop =
1052 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1054 /* make sure pll3 is enabled */
1055 if ((readl(&anatop->usb1_pll_480_ctrl) &
1056 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1057 /* enable pll's power */
1058 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1059 &anatop->usb1_pll_480_ctrl_set);
1060 writel(0x80, &anatop->ana_misc2_clr);
1061 /* wait for pll lock */
1062 while ((readl(&anatop->usb1_pll_480_ctrl) &
1063 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1065 /* disable bypass */
1066 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1067 &anatop->usb1_pll_480_ctrl_clr);
1068 /* enable pll output */
1069 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1070 &anatop->usb1_pll_480_ctrl_set);
1074 void enable_thermal_clk(void)
1079 unsigned int mxc_get_clock(enum mxc_clock clk)
1083 return get_mcu_main_clk();
1085 return get_periph_clk();
1087 return get_ahb_clk();
1089 return get_ipg_clk();
1090 case MXC_IPG_PERCLK:
1092 return get_ipg_per_clk();
1094 return get_uart_clk();
1096 return get_cspi_clk();
1098 return get_axi_clk();
1099 case MXC_EMI_SLOW_CLK:
1100 return get_emi_slow_clk();
1102 return get_mmdc_ch0_clk();
1104 return get_usdhc_clk(0);
1105 case MXC_ESDHC2_CLK:
1106 return get_usdhc_clk(1);
1107 case MXC_ESDHC3_CLK:
1108 return get_usdhc_clk(2);
1109 case MXC_ESDHC4_CLK:
1110 return get_usdhc_clk(3);
1112 return get_ahb_clk();
1114 printf("Unsupported MXC CLK: %d\n", clk);
1122 * Dump some core clockes.
1124 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1127 freq = decode_pll(PLL_SYS, MXC_HCLK);
1128 printf("PLL_SYS %8d MHz\n", freq / 1000000);
1129 freq = decode_pll(PLL_BUS, MXC_HCLK);
1130 printf("PLL_BUS %8d MHz\n", freq / 1000000);
1131 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1132 printf("PLL_OTG %8d MHz\n", freq / 1000000);
1133 freq = decode_pll(PLL_ENET, MXC_HCLK);
1134 printf("PLL_NET %8d MHz\n", freq / 1000000);
1137 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1138 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1139 #ifdef CONFIG_MXC_SPI
1140 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1142 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1143 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1144 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1145 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1146 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1147 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1148 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1149 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1150 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1155 #ifndef CONFIG_MX6SX
1156 void enable_ipu_clock(void)
1158 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1160 reg = readl(&mxc_ccm->CCGR3);
1161 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1162 writel(reg, &mxc_ccm->CCGR3);
1165 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1166 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1170 /***************************************************/
1173 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,