2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
16 PLL_SYS, /* System PLL */
17 PLL_BUS, /* System Bus PLL*/
18 PLL_USBOTG, /* OTG USB PLL */
19 PLL_ENET, /* ENET PLL */
22 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
24 #ifdef CONFIG_MXC_OCOTP
25 void enable_ocotp_clk(unsigned char enable)
29 reg = __raw_readl(&imx_ccm->CCGR2);
31 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
33 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 __raw_writel(reg, &imx_ccm->CCGR2);
38 void enable_usboh3_clk(unsigned char enable)
42 reg = __raw_readl(&imx_ccm->CCGR6);
44 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
46 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
47 __raw_writel(reg, &imx_ccm->CCGR6);
51 #ifdef CONFIG_SYS_I2C_MXC
52 /* i2c_num can be from 0 - 2 */
53 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
61 mask = MXC_CCM_CCGR_CG_MASK
62 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
63 reg = __raw_readl(&imx_ccm->CCGR2);
68 __raw_writel(reg, &imx_ccm->CCGR2);
73 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
79 div = __raw_readl(&imx_ccm->analog_pll_sys);
80 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
82 return infreq * (div >> 1);
84 div = __raw_readl(&imx_ccm->analog_pll_528);
85 div &= BM_ANADIG_PLL_528_DIV_SELECT;
87 return infreq * (20 + (div << 1));
89 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
90 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
92 return infreq * (20 + (div << 1));
94 div = __raw_readl(&imx_ccm->analog_pll_enet);
95 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
97 return (div == 3 ? 125000000 : 25000000 * (div << 1));
103 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
111 /* No PFD3 on PPL2 */
114 div = __raw_readl(&imx_ccm->analog_pfd_528);
115 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
118 div = __raw_readl(&imx_ccm->analog_pfd_480);
119 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
122 /* No PFD on other PLL */
126 return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
127 ANATOP_PFD_FRAC_SHIFT(pfd_num));
130 static u32 get_mcu_main_clk(void)
134 reg = __raw_readl(&imx_ccm->cacrr);
135 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
136 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
137 freq = decode_pll(PLL_SYS, MXC_HCLK);
139 return freq / (reg + 1);
142 u32 get_periph_clk(void)
146 reg = __raw_readl(&imx_ccm->cbcdr);
147 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
148 reg = __raw_readl(&imx_ccm->cbcmr);
149 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
150 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
154 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
164 reg = __raw_readl(&imx_ccm->cbcmr);
165 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
166 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
170 freq = decode_pll(PLL_BUS, MXC_HCLK);
173 freq = mxc_get_pll_pfd(PLL_BUS, 2);
176 freq = mxc_get_pll_pfd(PLL_BUS, 0);
179 /* static / 2 divider */
180 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
190 static u32 get_ipg_clk(void)
194 reg = __raw_readl(&imx_ccm->cbcdr);
195 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
196 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
198 return get_ahb_clk() / (ipg_podf + 1);
201 static u32 get_ipg_per_clk(void)
203 u32 reg, perclk_podf;
205 reg = __raw_readl(&imx_ccm->cscmr1);
206 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
208 return get_ipg_clk() / (perclk_podf + 1);
211 static u32 get_uart_clk(void)
214 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
215 reg = __raw_readl(&imx_ccm->cscdr1);
217 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
220 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
221 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
223 return freq / (uart_podf + 1);
226 static u32 get_cspi_clk(void)
230 reg = __raw_readl(&imx_ccm->cscdr2);
231 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
232 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
234 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
237 static u32 get_axi_clk(void)
239 u32 root_freq, axi_podf;
240 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
242 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
243 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
245 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
246 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
247 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
249 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
251 root_freq = get_periph_clk();
253 return root_freq / (axi_podf + 1);
256 static u32 get_emi_slow_clk(void)
258 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
260 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
261 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
262 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
263 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
264 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
266 switch (emi_clk_sel) {
268 root_freq = get_axi_clk();
271 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
274 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
277 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
281 return root_freq / (emi_slow_podf + 1);
285 static u32 get_mmdc_ch0_clk(void)
287 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
288 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
291 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
292 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
294 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
295 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
297 freq = decode_pll(PLL_BUS, MXC_HCLK);
300 freq = mxc_get_pll_pfd(PLL_BUS, 2);
303 freq = mxc_get_pll_pfd(PLL_BUS, 0);
306 /* static / 2 divider */
307 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
310 return freq / (podf + 1);
314 int enable_fec_anatop_clock(void)
317 s32 timeout = 100000;
319 struct anatop_regs __iomem *anatop =
320 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
322 reg = readl(&anatop->pll_enet);
323 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
324 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
325 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
326 writel(reg, &anatop->pll_enet);
328 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
335 /* Enable FEC clock */
336 reg |= BM_ANADIG_PLL_ENET_ENABLE;
337 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
338 writel(reg, &anatop->pll_enet);
344 static u32 get_mmdc_ch0_clk(void)
346 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
347 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
348 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
350 return get_periph_clk() / (mmdc_ch0_podf + 1);
354 static u32 get_usdhc_clk(u32 port)
356 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
357 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
358 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
362 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
363 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
364 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
368 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
369 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
370 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
374 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
375 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
376 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
380 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
381 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
382 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
390 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
392 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
394 return root_freq / (usdhc_podf + 1);
397 u32 imx_get_uartclk(void)
399 return get_uart_clk();
402 u32 imx_get_fecclk(void)
404 return decode_pll(PLL_ENET, MXC_HCLK);
407 int enable_sata_clock(void)
410 s32 timeout = 100000;
411 struct mxc_ccm_reg *const imx_ccm
412 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
414 /* Enable sata clock */
415 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
416 reg |= MXC_CCM_CCGR5_SATA_MASK;
417 writel(reg, &imx_ccm->CCGR5);
420 reg = readl(&imx_ccm->analog_pll_enet);
421 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
422 writel(reg, &imx_ccm->analog_pll_enet);
423 reg |= BM_ANADIG_PLL_SYS_ENABLE;
425 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
430 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
431 writel(reg, &imx_ccm->analog_pll_enet);
432 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
433 writel(reg, &imx_ccm->analog_pll_enet);
438 unsigned int mxc_get_clock(enum mxc_clock clk)
442 return get_mcu_main_clk();
444 return get_periph_clk();
446 return get_ahb_clk();
448 return get_ipg_clk();
451 return get_ipg_per_clk();
453 return get_uart_clk();
455 return get_cspi_clk();
457 return get_axi_clk();
458 case MXC_EMI_SLOW_CLK:
459 return get_emi_slow_clk();
461 return get_mmdc_ch0_clk();
463 return get_usdhc_clk(0);
465 return get_usdhc_clk(1);
467 return get_usdhc_clk(2);
469 return get_usdhc_clk(3);
471 return get_ahb_clk();
480 * Dump some core clockes.
482 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
485 freq = decode_pll(PLL_SYS, MXC_HCLK);
486 printf("PLL_SYS %8d MHz\n", freq / 1000000);
487 freq = decode_pll(PLL_BUS, MXC_HCLK);
488 printf("PLL_BUS %8d MHz\n", freq / 1000000);
489 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
490 printf("PLL_OTG %8d MHz\n", freq / 1000000);
491 freq = decode_pll(PLL_ENET, MXC_HCLK);
492 printf("PLL_NET %8d MHz\n", freq / 1000000);
495 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
496 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
497 #ifdef CONFIG_MXC_SPI
498 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
500 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
501 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
502 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
503 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
504 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
505 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
506 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
507 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
508 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
513 void enable_ipu_clock(void)
515 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
517 reg = readl(&mxc_ccm->CCGR3);
518 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
519 writel(reg, &mxc_ccm->CCGR3);
521 /***************************************************/
524 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,