2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/errno.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
32 PLL_SYS, /* System PLL */
33 PLL_BUS, /* System Bus PLL*/
34 PLL_USBOTG, /* OTG USB PLL */
35 PLL_ENET, /* ENET PLL */
38 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
40 void enable_usboh3_clk(unsigned char enable)
44 reg = __raw_readl(&imx_ccm->CCGR6);
46 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
48 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
49 __raw_writel(reg, &imx_ccm->CCGR6);
54 /* i2c_num can be from 0 - 2 */
55 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
63 mask = MXC_CCM_CCGR_CG_MASK
64 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
65 reg = __raw_readl(&imx_ccm->CCGR2);
70 __raw_writel(reg, &imx_ccm->CCGR2);
75 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
81 div = __raw_readl(&imx_ccm->analog_pll_sys);
82 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
84 return infreq * (div >> 1);
86 div = __raw_readl(&imx_ccm->analog_pll_528);
87 div &= BM_ANADIG_PLL_528_DIV_SELECT;
89 return infreq * (20 + (div << 1));
91 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
92 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
94 return infreq * (20 + (div << 1));
96 div = __raw_readl(&imx_ccm->analog_pll_enet);
97 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
99 return (div == 3 ? 125000000 : 25000000 * (div << 1));
106 static u32 get_mcu_main_clk(void)
110 reg = __raw_readl(&imx_ccm->cacrr);
111 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
112 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
113 freq = decode_pll(PLL_SYS, MXC_HCLK);
115 return freq / (reg + 1);
118 u32 get_periph_clk(void)
122 reg = __raw_readl(&imx_ccm->cbcdr);
123 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
124 reg = __raw_readl(&imx_ccm->cbcmr);
125 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
126 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
130 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
140 reg = __raw_readl(&imx_ccm->cbcmr);
141 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
142 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
146 freq = decode_pll(PLL_BUS, MXC_HCLK);
149 freq = PLL2_PFD2_FREQ;
152 freq = PLL2_PFD0_FREQ;
155 freq = PLL2_PFD2_DIV_FREQ;
165 static u32 get_ipg_clk(void)
169 reg = __raw_readl(&imx_ccm->cbcdr);
170 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
171 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
173 return get_ahb_clk() / (ipg_podf + 1);
176 static u32 get_ipg_per_clk(void)
178 u32 reg, perclk_podf;
180 reg = __raw_readl(&imx_ccm->cscmr1);
181 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
183 return get_ipg_clk() / (perclk_podf + 1);
186 static u32 get_uart_clk(void)
190 reg = __raw_readl(&imx_ccm->cscdr1);
191 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
192 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
194 return PLL3_80M / (uart_podf + 1);
197 static u32 get_cspi_clk(void)
201 reg = __raw_readl(&imx_ccm->cscdr2);
202 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
203 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
205 return PLL3_60M / (cspi_podf + 1);
208 static u32 get_axi_clk(void)
210 u32 root_freq, axi_podf;
211 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
213 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
214 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
216 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
217 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
218 root_freq = PLL2_PFD2_FREQ;
220 root_freq = PLL3_PFD1_FREQ;
222 root_freq = get_periph_clk();
224 return root_freq / (axi_podf + 1);
227 static u32 get_emi_slow_clk(void)
229 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
231 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
232 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
233 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
234 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
235 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
237 switch (emi_clk_sel) {
239 root_freq = get_axi_clk();
242 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
245 root_freq = PLL2_PFD2_FREQ;
248 root_freq = PLL2_PFD0_FREQ;
252 return root_freq / (emi_slow_pof + 1);
255 static u32 get_mmdc_ch0_clk(void)
257 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
258 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
259 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
261 return get_periph_clk() / (mmdc_ch0_podf + 1);
264 static u32 get_usdhc_clk(u32 port)
266 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
267 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
268 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
272 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
273 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
274 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
278 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
279 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
280 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
284 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
285 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
286 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
290 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
291 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
292 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
300 root_freq = PLL2_PFD0_FREQ;
302 root_freq = PLL2_PFD2_FREQ;
304 return root_freq / (usdhc_podf + 1);
307 u32 imx_get_uartclk(void)
309 return get_uart_clk();
312 u32 imx_get_fecclk(void)
314 return decode_pll(PLL_ENET, MXC_HCLK);
317 int enable_sata_clock(void)
320 s32 timeout = 100000;
321 struct mxc_ccm_reg *const imx_ccm
322 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
324 /* Enable sata clock */
325 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
326 reg |= MXC_CCM_CCGR5_SATA_MASK;
327 writel(reg, &imx_ccm->CCGR5);
330 reg = readl(&imx_ccm->analog_pll_enet);
331 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
332 writel(reg, &imx_ccm->analog_pll_enet);
333 reg |= BM_ANADIG_PLL_SYS_ENABLE;
335 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
340 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
341 writel(reg, &imx_ccm->analog_pll_enet);
342 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
343 writel(reg, &imx_ccm->analog_pll_enet);
348 unsigned int mxc_get_clock(enum mxc_clock clk)
352 return get_mcu_main_clk();
354 return get_periph_clk();
356 return get_ahb_clk();
358 return get_ipg_clk();
361 return get_ipg_per_clk();
363 return get_uart_clk();
365 return get_cspi_clk();
367 return get_axi_clk();
368 case MXC_EMI_SLOW_CLK:
369 return get_emi_slow_clk();
371 return get_mmdc_ch0_clk();
373 return get_usdhc_clk(0);
375 return get_usdhc_clk(1);
377 return get_usdhc_clk(2);
379 return get_usdhc_clk(3);
381 return get_ahb_clk();
390 * Dump some core clockes.
392 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
395 freq = decode_pll(PLL_SYS, MXC_HCLK);
396 printf("PLL_SYS %8d MHz\n", freq / 1000000);
397 freq = decode_pll(PLL_BUS, MXC_HCLK);
398 printf("PLL_BUS %8d MHz\n", freq / 1000000);
399 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
400 printf("PLL_OTG %8d MHz\n", freq / 1000000);
401 freq = decode_pll(PLL_ENET, MXC_HCLK);
402 printf("PLL_NET %8d MHz\n", freq / 1000000);
405 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
406 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
407 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
408 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
409 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
410 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
411 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
412 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
413 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
414 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
415 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
416 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
421 /***************************************************/
424 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,