2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
30 reg = __raw_readl(&imx_ccm->CCGR2);
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
39 void enable_usboh3_clk(unsigned char enable)
43 reg = __raw_readl(&imx_ccm->CCGR6);
45 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
47 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
48 __raw_writel(reg, &imx_ccm->CCGR6);
52 #ifdef CONFIG_SYS_I2C_MXC
53 /* i2c_num can be from 0 - 2 */
54 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
62 mask = MXC_CCM_CCGR_CG_MASK
63 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
64 reg = __raw_readl(&imx_ccm->CCGR2);
69 __raw_writel(reg, &imx_ccm->CCGR2);
74 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
80 div = __raw_readl(&imx_ccm->analog_pll_sys);
81 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
83 return infreq * (div >> 1);
85 div = __raw_readl(&imx_ccm->analog_pll_528);
86 div &= BM_ANADIG_PLL_528_DIV_SELECT;
88 return infreq * (20 + (div << 1));
90 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
91 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
93 return infreq * (20 + (div << 1));
95 div = __raw_readl(&imx_ccm->analog_pll_enet);
96 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
98 return 25000000 * (div + (div >> 1) + 1);
104 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
112 /* No PFD3 on PPL2 */
115 div = __raw_readl(&imx_ccm->analog_pfd_528);
116 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
119 div = __raw_readl(&imx_ccm->analog_pfd_480);
120 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
123 /* No PFD on other PLL */
127 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
128 ANATOP_PFD_FRAC_SHIFT(pfd_num));
131 static u32 get_mcu_main_clk(void)
135 reg = __raw_readl(&imx_ccm->cacrr);
136 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
137 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
138 freq = decode_pll(PLL_SYS, MXC_HCLK);
140 return freq / (reg + 1);
143 u32 get_periph_clk(void)
147 reg = __raw_readl(&imx_ccm->cbcdr);
148 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
149 reg = __raw_readl(&imx_ccm->cbcmr);
150 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
151 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
155 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
165 reg = __raw_readl(&imx_ccm->cbcmr);
166 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
167 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
171 freq = decode_pll(PLL_BUS, MXC_HCLK);
174 freq = mxc_get_pll_pfd(PLL_BUS, 2);
177 freq = mxc_get_pll_pfd(PLL_BUS, 0);
180 /* static / 2 divider */
181 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
191 static u32 get_ipg_clk(void)
195 reg = __raw_readl(&imx_ccm->cbcdr);
196 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
197 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
199 return get_ahb_clk() / (ipg_podf + 1);
202 static u32 get_ipg_per_clk(void)
204 u32 reg, perclk_podf;
206 reg = __raw_readl(&imx_ccm->cscmr1);
207 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
209 return get_ipg_clk() / (perclk_podf + 1);
212 static u32 get_uart_clk(void)
215 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
216 reg = __raw_readl(&imx_ccm->cscdr1);
218 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
221 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
222 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
224 return freq / (uart_podf + 1);
227 static u32 get_cspi_clk(void)
231 reg = __raw_readl(&imx_ccm->cscdr2);
232 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
233 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
235 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
238 static u32 get_axi_clk(void)
240 u32 root_freq, axi_podf;
241 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
243 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
244 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
246 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
247 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
248 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
250 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
252 root_freq = get_periph_clk();
254 return root_freq / (axi_podf + 1);
257 static u32 get_emi_slow_clk(void)
259 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
261 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
262 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
263 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
264 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
265 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
267 switch (emi_clk_sel) {
269 root_freq = get_axi_clk();
272 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
275 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
278 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
282 return root_freq / (emi_slow_podf + 1);
286 static u32 get_mmdc_ch0_clk(void)
288 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
289 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
292 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
293 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
295 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
296 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
298 freq = decode_pll(PLL_BUS, MXC_HCLK);
301 freq = mxc_get_pll_pfd(PLL_BUS, 2);
304 freq = mxc_get_pll_pfd(PLL_BUS, 0);
307 /* static / 2 divider */
308 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
311 return freq / (podf + 1);
315 static u32 get_mmdc_ch0_clk(void)
317 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
318 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
319 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
321 return get_periph_clk() / (mmdc_ch0_podf + 1);
325 #ifdef CONFIG_FEC_MXC
326 int enable_fec_anatop_clock(enum enet_freq freq)
329 s32 timeout = 100000;
331 struct anatop_regs __iomem *anatop =
332 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
334 if (freq < ENET_25MHz || freq > ENET_125MHz)
337 reg = readl(&anatop->pll_enet);
338 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
341 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
342 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
343 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
344 writel(reg, &anatop->pll_enet);
346 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
353 /* Enable FEC clock */
354 reg |= BM_ANADIG_PLL_ENET_ENABLE;
355 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
356 writel(reg, &anatop->pll_enet);
362 static u32 get_usdhc_clk(u32 port)
364 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
365 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
366 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
370 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
371 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
372 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
376 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
377 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
378 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
382 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
383 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
384 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
388 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
389 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
390 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
398 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
400 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
402 return root_freq / (usdhc_podf + 1);
405 u32 imx_get_uartclk(void)
407 return get_uart_clk();
410 u32 imx_get_fecclk(void)
412 return mxc_get_clock(MXC_IPG_CLK);
415 static int enable_enet_pll(uint32_t en)
417 struct mxc_ccm_reg *const imx_ccm
418 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
419 s32 timeout = 100000;
423 reg = readl(&imx_ccm->analog_pll_enet);
424 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
425 writel(reg, &imx_ccm->analog_pll_enet);
426 reg |= BM_ANADIG_PLL_SYS_ENABLE;
428 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
433 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
434 writel(reg, &imx_ccm->analog_pll_enet);
436 writel(reg, &imx_ccm->analog_pll_enet);
440 static void ungate_sata_clock(void)
442 struct mxc_ccm_reg *const imx_ccm =
443 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
445 /* Enable SATA clock. */
446 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
449 static void ungate_pcie_clock(void)
451 struct mxc_ccm_reg *const imx_ccm =
452 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
454 /* Enable PCIe clock. */
455 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
458 int enable_sata_clock(void)
461 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
464 int enable_pcie_clock(void)
466 struct anatop_regs *anatop_regs =
467 (struct anatop_regs *)ANATOP_BASE_ADDR;
468 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
473 * The register ANATOP_MISC1 is not documented in the Freescale
474 * MX6RM. The register that is mapped in the ANATOP space and
475 * marked as ANATOP_MISC1 is actually documented in the PMU section
476 * of the datasheet as PMU_MISC1.
478 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
479 * enable clock OUTPUT. This is important for PCI express link that
480 * is clocked from the i.MX6.
482 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
483 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
484 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
485 clrsetbits_le32(&anatop_regs->ana_misc1,
486 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
487 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
488 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
490 /* PCIe reference clock sourced from AXI. */
491 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
493 /* Party time! Ungate the clock to the PCIe. */
497 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
498 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
501 unsigned int mxc_get_clock(enum mxc_clock clk)
505 return get_mcu_main_clk();
507 return get_periph_clk();
509 return get_ahb_clk();
511 return get_ipg_clk();
514 return get_ipg_per_clk();
516 return get_uart_clk();
518 return get_cspi_clk();
520 return get_axi_clk();
521 case MXC_EMI_SLOW_CLK:
522 return get_emi_slow_clk();
524 return get_mmdc_ch0_clk();
526 return get_usdhc_clk(0);
528 return get_usdhc_clk(1);
530 return get_usdhc_clk(2);
532 return get_usdhc_clk(3);
534 return get_ahb_clk();
543 * Dump some core clockes.
545 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
548 freq = decode_pll(PLL_SYS, MXC_HCLK);
549 printf("PLL_SYS %8d MHz\n", freq / 1000000);
550 freq = decode_pll(PLL_BUS, MXC_HCLK);
551 printf("PLL_BUS %8d MHz\n", freq / 1000000);
552 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
553 printf("PLL_OTG %8d MHz\n", freq / 1000000);
554 freq = decode_pll(PLL_ENET, MXC_HCLK);
555 printf("PLL_NET %8d MHz\n", freq / 1000000);
558 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
559 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
560 #ifdef CONFIG_MXC_SPI
561 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
563 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
564 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
565 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
566 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
567 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
568 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
569 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
570 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
571 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
576 void enable_ipu_clock(void)
578 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
580 reg = readl(&mxc_ccm->CCGR3);
581 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
582 writel(reg, &mxc_ccm->CCGR3);
584 /***************************************************/
587 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,