2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/errno.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
32 PLL_SYS, /* System PLL */
33 PLL_BUS, /* System Bus PLL*/
34 PLL_USBOTG, /* OTG USB PLL */
35 PLL_ENET, /* ENET PLL */
38 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
40 void enable_usboh3_clk(unsigned char enable)
44 reg = __raw_readl(&imx_ccm->CCGR6);
46 reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
48 reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
49 __raw_writel(reg, &imx_ccm->CCGR6);
54 /* i2c_num can be from 0 - 2 */
55 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
62 mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
63 reg = __raw_readl(&imx_ccm->CCGR2);
68 __raw_writel(reg, &imx_ccm->CCGR2);
73 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
79 div = __raw_readl(&imx_ccm->analog_pll_sys);
80 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
82 return infreq * (div >> 1);
84 div = __raw_readl(&imx_ccm->analog_pll_528);
85 div &= BM_ANADIG_PLL_528_DIV_SELECT;
87 return infreq * (20 + (div << 1));
89 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
90 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
92 return infreq * (20 + (div << 1));
94 div = __raw_readl(&imx_ccm->analog_pll_enet);
95 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
97 return (div == 3 ? 125000000 : 25000000 * (div << 1));
104 static u32 get_mcu_main_clk(void)
108 reg = __raw_readl(&imx_ccm->cacrr);
109 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
110 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
111 freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
113 return freq / (reg + 1);
116 u32 get_periph_clk(void)
120 reg = __raw_readl(&imx_ccm->cbcdr);
121 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
122 reg = __raw_readl(&imx_ccm->cbcmr);
123 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
124 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
128 freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
132 freq = CONFIG_SYS_MX6_HCLK;
138 reg = __raw_readl(&imx_ccm->cbcmr);
139 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
140 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
144 freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
147 freq = PLL2_PFD2_FREQ;
150 freq = PLL2_PFD0_FREQ;
153 freq = PLL2_PFD2_DIV_FREQ;
163 static u32 get_ipg_clk(void)
167 reg = __raw_readl(&imx_ccm->cbcdr);
168 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
169 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
171 return get_ahb_clk() / (ipg_podf + 1);
174 static u32 get_ipg_per_clk(void)
176 u32 reg, perclk_podf;
178 reg = __raw_readl(&imx_ccm->cscmr1);
179 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
181 return get_ipg_clk() / (perclk_podf + 1);
184 static u32 get_uart_clk(void)
188 reg = __raw_readl(&imx_ccm->cscdr1);
189 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
190 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
192 return PLL3_80M / (uart_podf + 1);
195 static u32 get_cspi_clk(void)
199 reg = __raw_readl(&imx_ccm->cscdr2);
200 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
201 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
203 return PLL3_60M / (cspi_podf + 1);
206 static u32 get_axi_clk(void)
208 u32 root_freq, axi_podf;
209 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
211 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
212 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
214 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
215 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
216 root_freq = PLL2_PFD2_FREQ;
218 root_freq = PLL3_PFD1_FREQ;
220 root_freq = get_periph_clk();
222 return root_freq / (axi_podf + 1);
225 static u32 get_emi_slow_clk(void)
227 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
229 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
230 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
231 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
232 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
233 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
235 switch (emi_clk_sel) {
237 root_freq = get_axi_clk();
240 root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
243 root_freq = PLL2_PFD2_FREQ;
246 root_freq = PLL2_PFD0_FREQ;
250 return root_freq / (emi_slow_pof + 1);
253 static u32 get_mmdc_ch0_clk(void)
255 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
256 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
257 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
259 return get_periph_clk() / (mmdc_ch0_podf + 1);
262 static u32 get_usdhc_clk(u32 port)
264 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
265 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
266 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
270 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
271 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
272 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
276 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
277 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
278 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
282 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
283 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
284 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
288 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
289 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
290 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
298 root_freq = PLL2_PFD0_FREQ;
300 root_freq = PLL2_PFD2_FREQ;
302 return root_freq / (usdhc_podf + 1);
305 u32 imx_get_uartclk(void)
307 return get_uart_clk();
310 u32 imx_get_fecclk(void)
312 return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
315 int enable_sata_clock(void)
318 s32 timeout = 100000;
319 struct mxc_ccm_reg *const imx_ccm
320 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
322 /* Enable sata clock */
323 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
324 reg |= MXC_CCM_CCGR5_CG2_MASK;
325 writel(reg, &imx_ccm->CCGR5);
328 reg = readl(&imx_ccm->analog_pll_enet);
329 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
330 writel(reg, &imx_ccm->analog_pll_enet);
331 reg |= BM_ANADIG_PLL_SYS_ENABLE;
333 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
338 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
339 writel(reg, &imx_ccm->analog_pll_enet);
340 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
341 writel(reg, &imx_ccm->analog_pll_enet);
346 unsigned int mxc_get_clock(enum mxc_clock clk)
350 return get_mcu_main_clk();
352 return get_periph_clk();
354 return get_ahb_clk();
356 return get_ipg_clk();
358 return get_ipg_per_clk();
360 return get_uart_clk();
362 return get_cspi_clk();
364 return get_axi_clk();
365 case MXC_EMI_SLOW_CLK:
366 return get_emi_slow_clk();
368 return get_mmdc_ch0_clk();
370 return get_usdhc_clk(0);
372 return get_usdhc_clk(1);
374 return get_usdhc_clk(2);
376 return get_usdhc_clk(3);
378 return get_ahb_clk();
387 * Dump some core clockes.
389 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
392 freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
393 printf("PLL_SYS %8d MHz\n", freq / 1000000);
394 freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
395 printf("PLL_BUS %8d MHz\n", freq / 1000000);
396 freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
397 printf("PLL_OTG %8d MHz\n", freq / 1000000);
398 freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
399 printf("PLL_NET %8d MHz\n", freq / 1000000);
402 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
403 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
404 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
405 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
406 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
407 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
408 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
409 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
410 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
411 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
412 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
413 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
418 /***************************************************/
421 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,