2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/errno.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
32 PLL_SYS, /* System PLL */
33 PLL_BUS, /* System Bus PLL*/
34 PLL_USBOTG, /* OTG USB PLL */
35 PLL_ENET, /* ENET PLL */
38 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
40 void enable_usboh3_clk(unsigned char enable)
44 reg = __raw_readl(&imx_ccm->CCGR6);
46 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
48 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
49 __raw_writel(reg, &imx_ccm->CCGR6);
54 /* i2c_num can be from 0 - 2 */
55 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
63 mask = MXC_CCM_CCGR_CG_MASK
64 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
65 reg = __raw_readl(&imx_ccm->CCGR2);
70 __raw_writel(reg, &imx_ccm->CCGR2);
75 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
81 div = __raw_readl(&imx_ccm->analog_pll_sys);
82 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
84 return infreq * (div >> 1);
86 div = __raw_readl(&imx_ccm->analog_pll_528);
87 div &= BM_ANADIG_PLL_528_DIV_SELECT;
89 return infreq * (20 + (div << 1));
91 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
92 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
94 return infreq * (20 + (div << 1));
96 div = __raw_readl(&imx_ccm->analog_pll_enet);
97 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
99 return (div == 3 ? 125000000 : 25000000 * (div << 1));
106 static u32 get_mcu_main_clk(void)
110 reg = __raw_readl(&imx_ccm->cacrr);
111 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
112 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
113 freq = decode_pll(PLL_SYS, MXC_HCLK);
115 return freq / (reg + 1);
118 u32 get_periph_clk(void)
122 reg = __raw_readl(&imx_ccm->cbcdr);
123 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
124 reg = __raw_readl(&imx_ccm->cbcmr);
125 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
126 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
130 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
140 reg = __raw_readl(&imx_ccm->cbcmr);
141 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
142 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
146 freq = decode_pll(PLL_BUS, MXC_HCLK);
149 freq = PLL2_PFD2_FREQ;
152 freq = PLL2_PFD0_FREQ;
155 freq = PLL2_PFD2_DIV_FREQ;
165 static u32 get_ipg_clk(void)
169 reg = __raw_readl(&imx_ccm->cbcdr);
170 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
171 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
173 return get_ahb_clk() / (ipg_podf + 1);
176 static u32 get_ipg_per_clk(void)
178 u32 reg, perclk_podf;
180 reg = __raw_readl(&imx_ccm->cscmr1);
181 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
183 return get_ipg_clk() / (perclk_podf + 1);
186 static u32 get_uart_clk(void)
190 reg = __raw_readl(&imx_ccm->cscdr1);
192 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
195 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
196 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
198 return freq / (uart_podf + 1);
201 static u32 get_cspi_clk(void)
205 reg = __raw_readl(&imx_ccm->cscdr2);
206 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
207 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
209 return PLL3_60M / (cspi_podf + 1);
212 static u32 get_axi_clk(void)
214 u32 root_freq, axi_podf;
215 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
217 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
218 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
220 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
221 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
222 root_freq = PLL2_PFD2_FREQ;
224 root_freq = PLL3_PFD1_FREQ;
226 root_freq = get_periph_clk();
228 return root_freq / (axi_podf + 1);
231 static u32 get_emi_slow_clk(void)
233 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
235 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
236 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
237 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
238 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
239 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
241 switch (emi_clk_sel) {
243 root_freq = get_axi_clk();
246 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
249 root_freq = PLL2_PFD2_FREQ;
252 root_freq = PLL2_PFD0_FREQ;
256 return root_freq / (emi_slow_pof + 1);
260 static u32 get_mmdc_ch0_clk(void)
262 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
263 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
266 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
267 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
269 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
270 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
272 freq = decode_pll(PLL_BUS, MXC_HCLK);
275 freq = PLL2_PFD2_FREQ;
278 freq = PLL2_PFD0_FREQ;
281 freq = PLL2_PFD2_DIV_FREQ;
284 return freq / (podf + 1);
288 static u32 get_mmdc_ch0_clk(void)
290 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
291 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
292 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
294 return get_periph_clk() / (mmdc_ch0_podf + 1);
298 static u32 get_usdhc_clk(u32 port)
300 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
301 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
302 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
306 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
307 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
308 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
312 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
313 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
314 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
318 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
319 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
320 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
324 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
325 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
326 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
334 root_freq = PLL2_PFD0_FREQ;
336 root_freq = PLL2_PFD2_FREQ;
338 return root_freq / (usdhc_podf + 1);
341 u32 imx_get_uartclk(void)
343 return get_uart_clk();
346 u32 imx_get_fecclk(void)
348 return decode_pll(PLL_ENET, MXC_HCLK);
351 int enable_sata_clock(void)
354 s32 timeout = 100000;
355 struct mxc_ccm_reg *const imx_ccm
356 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
358 /* Enable sata clock */
359 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
360 reg |= MXC_CCM_CCGR5_SATA_MASK;
361 writel(reg, &imx_ccm->CCGR5);
364 reg = readl(&imx_ccm->analog_pll_enet);
365 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
366 writel(reg, &imx_ccm->analog_pll_enet);
367 reg |= BM_ANADIG_PLL_SYS_ENABLE;
369 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
374 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
375 writel(reg, &imx_ccm->analog_pll_enet);
376 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
377 writel(reg, &imx_ccm->analog_pll_enet);
382 unsigned int mxc_get_clock(enum mxc_clock clk)
386 return get_mcu_main_clk();
388 return get_periph_clk();
390 return get_ahb_clk();
392 return get_ipg_clk();
395 return get_ipg_per_clk();
397 return get_uart_clk();
399 return get_cspi_clk();
401 return get_axi_clk();
402 case MXC_EMI_SLOW_CLK:
403 return get_emi_slow_clk();
405 return get_mmdc_ch0_clk();
407 return get_usdhc_clk(0);
409 return get_usdhc_clk(1);
411 return get_usdhc_clk(2);
413 return get_usdhc_clk(3);
415 return get_ahb_clk();
424 * Dump some core clockes.
426 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
429 freq = decode_pll(PLL_SYS, MXC_HCLK);
430 printf("PLL_SYS %8d MHz\n", freq / 1000000);
431 freq = decode_pll(PLL_BUS, MXC_HCLK);
432 printf("PLL_BUS %8d MHz\n", freq / 1000000);
433 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
434 printf("PLL_OTG %8d MHz\n", freq / 1000000);
435 freq = decode_pll(PLL_ENET, MXC_HCLK);
436 printf("PLL_NET %8d MHz\n", freq / 1000000);
439 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
440 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
441 #ifdef CONFIG_MXC_SPI
442 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
444 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
445 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
446 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
447 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
448 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
449 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
450 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
451 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
452 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
457 /***************************************************/
460 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,