git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_SYS,        /* System PLL */
  18         PLL_BUS,        /* System Bus PLL*/
  19         PLL_USBOTG,     /* OTG USB PLL */
  20         PLL_ENET,       /* ENET PLL */
  21         PLL_AUDIO,      /* AUDIO PLL */
  22         PLL_VIDEO,      /* AUDIO PLL */
  23 };
  24
  25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  26
  27 #ifdef CONFIG_MXC_OCOTP
  28 void enable_ocotp_clk(unsigned char enable)
  29 {
  30         u32 reg;
  31
  32         reg = __raw_readl(&imx_ccm->CCGR2);
  33         if (enable)
  34                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  35         else
  36                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  37         __raw_writel(reg, &imx_ccm->CCGR2);
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_NAND_MXS
  42 void setup_gpmi_io_clk(u32 cfg)
  43 {
  44         /* Disable clocks per ERR007177 from MX6 errata */
  45         clrbits_le32(&imx_ccm->CCGR4,
  46                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  47                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  48                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  49                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  50                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  51
  52 #if defined(CONFIG_MX6SX)
  53         clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  54
  55         clrsetbits_le32(&imx_ccm->cs2cdr,
  56                         MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  57                         MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  58                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  59                         cfg);
  60
  61         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  62 #else
  63         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  64
  65         clrsetbits_le32(&imx_ccm->cs2cdr,
  66                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  67                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  68                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  69                         cfg);
  70
  71         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  72 #endif
  73         setbits_le32(&imx_ccm->CCGR4,
  74                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  77                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  78                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  79 }
  80 #endif
  81
  82 void enable_usboh3_clk(unsigned char enable)
  83 {
  84         u32 reg;
  85
  86         reg = __raw_readl(&imx_ccm->CCGR6);
  87         if (enable)
  88                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  89         else
  90                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  91         __raw_writel(reg, &imx_ccm->CCGR6);
  92
  93 }
  94
  95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  96 void enable_enet_clk(unsigned char enable)
  97 {
  98         u32 mask, *addr;
  99
 100         if (is_mx6ull()) {
 101                 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
 102                 addr = &imx_ccm->CCGR0;
 103         } else if (is_mx6ul()) {
 104                 mask = MXC_CCM_CCGR3_ENET_MASK;
 105                 addr = &imx_ccm->CCGR3;
 106         } else {
 107                 mask = MXC_CCM_CCGR1_ENET_MASK;
 108                 addr = &imx_ccm->CCGR1;
 109         }
 110
 111         if (enable)
 112                 setbits_le32(addr, mask);
 113         else
 114                 clrbits_le32(addr, mask);
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_MXC_UART
 119 void enable_uart_clk(unsigned char enable)
 120 {
 121         u32 mask;
 122
 123         if (is_mx6ul() || is_mx6ull())
 124                 mask = MXC_CCM_CCGR5_UART_MASK;
 125         else
 126                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 127
 128         if (enable)
 129                 setbits_le32(&imx_ccm->CCGR5, mask);
 130         else
 131                 clrbits_le32(&imx_ccm->CCGR5, mask);
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_MMC
 136 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 137 {
 138         u32 mask;
 139
 140         if (bus_num > 3)
 141                 return -EINVAL;
 142
 143         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 144         if (enable)
 145                 setbits_le32(&imx_ccm->CCGR6, mask);
 146         else
 147                 clrbits_le32(&imx_ccm->CCGR6, mask);
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_SYS_I2C_MXC
 154 /* i2c_num can be from 0 - 3 */
 155 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 156 {
 157         u32 reg;
 158         u32 mask;
 159         u32 *addr;
 160
 161         if (i2c_num > 3)
 162                 return -EINVAL;
 163         if (i2c_num < 3) {
 164                 mask = MXC_CCM_CCGR_CG_MASK
 165                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 166                         + (i2c_num << 1));
 167                 reg = __raw_readl(&imx_ccm->CCGR2);
 168                 if (enable)
 169                         reg |= mask;
 170                 else
 171                         reg &= ~mask;
 172                 __raw_writel(reg, &imx_ccm->CCGR2);
 173         } else {
 174                 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
 175                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 176                         addr = &imx_ccm->CCGR6;
 177                 } else {
 178                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 179                         addr = &imx_ccm->CCGR1;
 180                 }
 181                 reg = __raw_readl(addr);
 182                 if (enable)
 183                         reg |= mask;
 184                 else
 185                         reg &= ~mask;
 186                 __raw_writel(reg, addr);
 187         }
 188         return 0;
 189 }
 190 #endif
 191
 192 /* spi_num can be from 0 - SPI_MAX_NUM */
 193 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 194 {
 195         u32 reg;
 196         u32 mask;
 197
 198         if (spi_num > SPI_MAX_NUM)
 199                 return -EINVAL;
 200
 201         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 202         reg = __raw_readl(&imx_ccm->CCGR1);
 203         if (enable)
 204                 reg |= mask;
 205         else
 206                 reg &= ~mask;
 207         __raw_writel(reg, &imx_ccm->CCGR1);
 208         return 0;
 209 }
 210 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 211 {
 212         u32 div, test_div, pll_num, pll_denom;
 213
 214         switch (pll) {
 215         case PLL_SYS:
 216                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 217                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 218
 219                 return (infreq * div) >> 1;
 220         case PLL_BUS:
 221                 div = __raw_readl(&imx_ccm->analog_pll_528);
 222                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 223
 224                 return infreq * (20 + (div << 1));
 225         case PLL_USBOTG:
 226                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 227                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 228
 229                 return infreq * (20 + (div << 1));
 230         case PLL_ENET:
 231                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 232                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 233
 234                 return 25000000 * (div + (div >> 1) + 1);
 235         case PLL_AUDIO:
 236                 div = __raw_readl(&imx_ccm->analog_pll_audio);
 237                 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
 238                         return 0;
 239                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 240                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 241                         return MXC_HCLK;
 242                 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
 243                 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
 244                 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
 245                         BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
 246                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 247                 if (test_div == 3) {
 248                         debug("Error test_div\n");
 249                         return 0;
 250                 }
 251                 test_div = 1 << (2 - test_div);
 252
 253                 return infreq * (div + pll_num / pll_denom) / test_div;
 254         case PLL_VIDEO:
 255                 div = __raw_readl(&imx_ccm->analog_pll_video);
 256                 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
 257                         return 0;
 258                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 259                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 260                         return MXC_HCLK;
 261                 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
 262                 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
 263                 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 264                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 265                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 266                 if (test_div == 3) {
 267                         debug("Error test_div\n");
 268                         return 0;
 269                 }
 270                 test_div = 1 << (2 - test_div);
 271
 272                 return infreq * (div + pll_num / pll_denom) / test_div;
 273         default:
 274                 return 0;
 275         }
 276         /* NOTREACHED */
 277 }
 278 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 279 {
 280         u32 div;
 281         u64 freq;
 282
 283         switch (pll) {
 284         case PLL_BUS:
 285                 if (!is_mx6ul() && !is_mx6ull()) {
 286                         if (pfd_num == 3) {
 287                                 /* No PFD3 on PLL2 */
 288                                 return 0;
 289                         }
 290                 }
 291                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 292                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 293                 break;
 294         case PLL_USBOTG:
 295                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 296                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 297                 break;
 298         default:
 299                 /* No PFD on other PLL                                       */
 300                 return 0;
 301         }
 302
 303         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 304                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 305 }
 306
 307 static u32 get_mcu_main_clk(void)
 308 {
 309         u32 reg, freq;
 310
 311         reg = __raw_readl(&imx_ccm->cacrr);
 312         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 313         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 314         freq = decode_pll(PLL_SYS, MXC_HCLK);
 315
 316         return freq / (reg + 1);
 317 }
 318
 319 u32 get_periph_clk(void)
 320 {
 321         u32 reg, div = 0, freq = 0;
 322
 323         reg = __raw_readl(&imx_ccm->cbcdr);
 324         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 325                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 326                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 327                 reg = __raw_readl(&imx_ccm->cbcmr);
 328                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 329                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 330
 331                 switch (reg) {
 332                 case 0:
 333                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 334                         break;
 335                 case 1:
 336                 case 2:
 337                         freq = MXC_HCLK;
 338                         break;
 339                 default:
 340                         break;
 341                 }
 342         } else {
 343                 reg = __raw_readl(&imx_ccm->cbcmr);
 344                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 345                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 346
 347                 switch (reg) {
 348                 case 0:
 349                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 350                         break;
 351                 case 1:
 352                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 353                         break;
 354                 case 2:
 355                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 356                         break;
 357                 case 3:
 358                         /* static / 2 divider */
 359                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 360                         break;
 361                 default:
 362                         break;
 363                 }
 364         }
 365
 366         return freq / (div + 1);
 367 }
 368
 369 static u32 get_ipg_clk(void)
 370 {
 371         u32 reg, ipg_podf;
 372
 373         reg = __raw_readl(&imx_ccm->cbcdr);
 374         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 375         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 376
 377         return get_ahb_clk() / (ipg_podf + 1);
 378 }
 379
 380 static u32 get_ipg_per_clk(void)
 381 {
 382         u32 reg, perclk_podf;
 383
 384         reg = __raw_readl(&imx_ccm->cscmr1);
 385         if (is_mx6sl() || is_mx6sx() ||
 386             is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
 387                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 388                         return MXC_HCLK; /* OSC 24Mhz */
 389         }
 390
 391         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 392
 393         return get_ipg_clk() / (perclk_podf + 1);
 394 }
 395
 396 static u32 get_uart_clk(void)
 397 {
 398         u32 reg, uart_podf;
 399         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 400         reg = __raw_readl(&imx_ccm->cscdr1);
 401
 402         if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
 403             is_mx6ull()) {
 404                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 405                         freq = MXC_HCLK;
 406         }
 407
 408         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 409         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 410
 411         return freq / (uart_podf + 1);
 412 }
 413
 414 static u32 get_cspi_clk(void)
 415 {
 416         u32 reg, cspi_podf;
 417
 418         reg = __raw_readl(&imx_ccm->cscdr2);
 419         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 420                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 421
 422         if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
 423             is_mx6ull()) {
 424                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 425                         return MXC_HCLK / (cspi_podf + 1);
 426         }
 427
 428         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 429 }
 430
 431 static u32 get_axi_clk(void)
 432 {
 433         u32 root_freq, axi_podf;
 434         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 435
 436         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 437         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 438
 439         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 440                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 441                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 442                 else
 443                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 444         } else
 445                 root_freq = get_periph_clk();
 446
 447         return  root_freq / (axi_podf + 1);
 448 }
 449
 450 static u32 get_emi_slow_clk(void)
 451 {
 452         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 453
 454         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 455         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 456         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 457         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 458         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 459
 460         switch (emi_clk_sel) {
 461         case 0:
 462                 root_freq = get_axi_clk();
 463                 break;
 464         case 1:
 465                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 466                 break;
 467         case 2:
 468                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 469                 break;
 470         case 3:
 471                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 472                 break;
 473         }
 474
 475         return root_freq / (emi_slow_podf + 1);
 476 }
 477
 478 static u32 get_mmdc_ch0_clk(void)
 479 {
 480         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 481         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 482
 483         u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 484
 485         if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
 486                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 487                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 488                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 489                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 490                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 491                         if (is_mx6sl()) {
 492                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 493                                         freq = MXC_HCLK;
 494                                 else
 495                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 496                         } else {
 497                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 498                                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 499                                 else
 500                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 501                         }
 502                 } else {
 503                         per2_clk2_podf = 0;
 504                         switch ((cbcmr &
 505                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 506                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 507                         case 0:
 508                                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 509                                 break;
 510                         case 1:
 511                                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 512                                 break;
 513                         case 2:
 514                                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 515                                 break;
 516                         case 3:
 517                                 if (is_mx6sl()) {
 518                                         freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
 519                                         break;
 520                                 }
 521
 522                                 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
 523                                 switch (pmu_misc2_audio_div) {
 524                                 case 0:
 525                                 case 2:
 526                                         pmu_misc2_audio_div = 1;
 527                                         break;
 528                                 case 1:
 529                                         pmu_misc2_audio_div = 2;
 530                                         break;
 531                                 case 3:
 532                                         pmu_misc2_audio_div = 4;
 533                                         break;
 534                                 }
 535                                 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
 536                                         pmu_misc2_audio_div;
 537                                 break;
 538                         }
 539                 }
 540                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 541         } else {
 542                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 543                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 544                 return get_periph_clk() / (podf + 1);
 545         }
 546 }
 547
 548 #if defined(CONFIG_VIDEO_MXS)
 549 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
 550                             u32 post_div)
 551 {
 552         u32 reg = 0;
 553         ulong start;
 554
 555         debug("pll5 div = %d, num = %d, denom = %d\n",
 556               pll_div, pll_num, pll_denom);
 557
 558         /* Power up PLL5 video */
 559         writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
 560                BM_ANADIG_PLL_VIDEO_BYPASS |
 561                BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 562                BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 563                &imx_ccm->analog_pll_video_clr);
 564
 565         /* Set div, num and denom */
 566         switch (post_div) {
 567         case 1:
 568                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 569                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
 570                        &imx_ccm->analog_pll_video_set);
 571                 break;
 572         case 2:
 573                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 574                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
 575                        &imx_ccm->analog_pll_video_set);
 576                 break;
 577         case 4:
 578                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 579                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
 580                        &imx_ccm->analog_pll_video_set);
 581                 break;
 582         default:
 583                 puts("Wrong test_div!\n");
 584                 return -EINVAL;
 585         }
 586
 587         writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
 588                &imx_ccm->analog_pll_video_num);
 589         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
 590                &imx_ccm->analog_pll_video_denom);
 591
 592         /* Wait PLL5 lock */
 593         start = get_timer(0);   /* Get current timestamp */
 594
 595         do {
 596                 reg = readl(&imx_ccm->analog_pll_video);
 597                 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
 598                         /* Enable PLL out */
 599                         writel(BM_ANADIG_PLL_VIDEO_ENABLE,
 600                                &imx_ccm->analog_pll_video_set);
 601                         return 0;
 602                 }
 603         } while (get_timer(0) < (start + 10)); /* Wait 10ms */
 604
 605         puts("Lock PLL5 timeout\n");
 606
 607         return -ETIME;
 608 }
 609
 610 /*
 611  * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
 612  *
 613  * 'freq' using KHz as unit, see driver/video/mxsfb.c.
 614  */
 615 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 616 {
 617         u32 reg = 0;
 618         u32 hck = MXC_HCLK / 1000;
 619         /* DIV_SELECT ranges from 27 to 54 */
 620         u32 min = hck * 27;
 621         u32 max = hck * 54;
 622         u32 temp, best = 0;
 623         u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
 624         u32 pll_div, pll_num, pll_denom, post_div = 1;
 625
 626         debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 627
 628         if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
 629                 debug("This chip not support lcd!\n");
 630                 return;
 631         }
 632
 633         if (!is_mx6sl()) {
 634                 if (base_addr == LCDIF1_BASE_ADDR) {
 635                         reg = readl(&imx_ccm->cscdr2);
 636                         /* Can't change clocks when clock not from pre-mux */
 637                         if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
 638                                 return;
 639                 }
 640         }
 641
 642         if (is_mx6sx()) {
 643                 reg = readl(&imx_ccm->cscdr2);
 644                 /* Can't change clocks when clock not from pre-mux */
 645                 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
 646                         return;
 647         }
 648
 649         temp = freq * max_pred * max_postd;
 650         if (temp < min) {
 651                 /*
 652                  * Register: PLL_VIDEO
 653                  * Bit Field: POST_DIV_SELECT
 654                  * 00 — Divide by 4.
 655                  * 01 — Divide by 2.
 656                  * 10 — Divide by 1.
 657                  * 11 — Reserved
 658                  * No need to check post_div(1)
 659                  */
 660                 for (post_div = 2; post_div <= 4; post_div <<= 1) {
 661                         if ((temp * post_div) > min) {
 662                                 freq *= post_div;
 663                                 break;
 664                         }
 665                 }
 666
 667                 if (post_div > 4) {
 668                         printf("Fail to set rate to %dkhz", freq);
 669                         return;
 670                 }
 671         }
 672
 673         /* Choose the best pred and postd to match freq for lcd */
 674         for (i = 1; i <= max_pred; i++) {
 675                 for (j = 1; j <= max_postd; j++) {
 676                         temp = freq * i * j;
 677                         if (temp > max || temp < min)
 678                                 continue;
 679                         if (best == 0 || temp < best) {
 680                                 best = temp;
 681                                 pred = i;
 682                                 postd = j;
 683                         }
 684                 }
 685         }
 686
 687         if (best == 0) {
 688                 printf("Fail to set rate to %dKHz", freq);
 689                 return;
 690         }
 691
 692         debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
 693
 694         pll_div = best / hck;
 695         pll_denom = 1000000;
 696         pll_num = (best - hck * pll_div) * pll_denom / hck;
 697
 698         /*
 699          *                                  pll_num
 700          *             (24MHz * (pll_div + --------- ))
 701          *                                 pll_denom
 702          *freq KHz =  --------------------------------
 703          *             post_div * pred * postd * 1000
 704          */
 705
 706         if (base_addr == LCDIF1_BASE_ADDR) {
 707                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 708                         return;
 709
 710                 enable_lcdif_clock(base_addr, 0);
 711                 if (!is_mx6sl()) {
 712                         /* Select pre-lcd clock to PLL5 and set pre divider */
 713                         clrsetbits_le32(&imx_ccm->cscdr2,
 714                                         MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
 715                                         MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
 716                                         (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
 717                                         ((pred - 1) <<
 718                                          MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
 719
 720                         /* Set the post divider */
 721                         clrsetbits_le32(&imx_ccm->cbcmr,
 722                                         MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 723                                         ((postd - 1) <<
 724                                         MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
 725                 } else {
 726                         /* Select pre-lcd clock to PLL5 and set pre divider */
 727                         clrsetbits_le32(&imx_ccm->cscdr2,
 728                                         MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
 729                                         MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
 730                                         (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
 731                                         ((pred - 1) <<
 732                                          MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
 733
 734                         /* Set the post divider */
 735                         clrsetbits_le32(&imx_ccm->cscmr1,
 736                                         MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
 737                                         (((postd - 1)^0x6) <<
 738                                          MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
 739                 }
 740
 741                 enable_lcdif_clock(base_addr, 1);
 742         } else if (is_mx6sx()) {
 743                 /* Setting LCDIF2 for i.MX6SX */
 744                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 745                         return;
 746
 747                 enable_lcdif_clock(base_addr, 0);
 748                 /* Select pre-lcd clock to PLL5 and set pre divider */
 749                 clrsetbits_le32(&imx_ccm->cscdr2,
 750                                 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
 751                                 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
 752                                 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
 753                                 ((pred - 1) <<
 754                                  MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
 755
 756                 /* Set the post divider */
 757                 clrsetbits_le32(&imx_ccm->cscmr1,
 758                                 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
 759                                 ((postd - 1) <<
 760                                  MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 761
 762                 enable_lcdif_clock(base_addr, 1);
 763         }
 764 }
 765
 766 int enable_lcdif_clock(u32 base_addr, bool enable)
 767 {
 768         u32 reg = 0;
 769         u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 770
 771         if (is_mx6sx()) {
 772                 if ((base_addr != LCDIF1_BASE_ADDR) &&
 773                     (base_addr != LCDIF2_BASE_ADDR)) {
 774                         puts("Wrong LCD interface!\n");
 775                         return -EINVAL;
 776                 }
 777                 /* Set to pre-mux clock at default */
 778                 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 779                         MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
 780                         MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 781                 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 782                         (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
 783                          MXC_CCM_CCGR3_DISP_AXI_MASK) :
 784                         (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 785                          MXC_CCM_CCGR3_DISP_AXI_MASK);
 786         } else if (is_mx6ul() || is_mx6ull()) {
 787                 if (base_addr != LCDIF1_BASE_ADDR) {
 788                         puts("Wrong LCD interface!\n");
 789                         return -EINVAL;
 790                 }
 791                 /* Set to pre-mux clock at default */
 792                 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 793                 lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
 794         } else if (is_mx6sl()) {
 795                 if (base_addr != LCDIF1_BASE_ADDR) {
 796                         puts("Wrong LCD interface!\n");
 797                         return -EINVAL;
 798                 }
 799
 800                 reg = readl(&imx_ccm->CCGR3);
 801                 reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
 802                          MXC_CCM_CCGR3_LCDIF_PIX_MASK);
 803                 writel(reg, &imx_ccm->CCGR3);
 804
 805                 if (enable) {
 806                         reg = readl(&imx_ccm->cscdr3);
 807                         reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
 808                         reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
 809                         writel(reg, &imx_ccm->cscdr3);
 810
 811                         reg = readl(&imx_ccm->CCGR3);
 812                         reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
 813                                 MXC_CCM_CCGR3_LCDIF_PIX_MASK;
 814                         writel(reg, &imx_ccm->CCGR3);
 815                 }
 816
 817                 return 0;
 818         } else {
 819                 return 0;
 820         }
 821
 822         /* Gate LCDIF clock first */
 823         reg = readl(&imx_ccm->CCGR3);
 824         reg &= ~lcdif_ccgr3_mask;
 825         writel(reg, &imx_ccm->CCGR3);
 826
 827         reg = readl(&imx_ccm->CCGR2);
 828         reg &= ~MXC_CCM_CCGR2_LCD_MASK;
 829         writel(reg, &imx_ccm->CCGR2);
 830
 831         if (enable) {
 832                 /* Select pre-mux */
 833                 reg = readl(&imx_ccm->cscdr2);
 834                 reg &= ~lcdif_clk_sel_mask;
 835                 writel(reg, &imx_ccm->cscdr2);
 836
 837                 /* Enable the LCDIF pix clock */
 838                 reg = readl(&imx_ccm->CCGR3);
 839                 reg |= lcdif_ccgr3_mask;
 840                 writel(reg, &imx_ccm->CCGR3);
 841
 842                 reg = readl(&imx_ccm->CCGR2);
 843                 reg |= MXC_CCM_CCGR2_LCD_MASK;
 844                 writel(reg, &imx_ccm->CCGR2);
 845         }
 846
 847         return 0;
 848 }
 849 #endif
 850
 851 #ifdef CONFIG_FSL_QSPI
 852 /* qspi_num can be from 0 - 1 */
 853 void enable_qspi_clk(int qspi_num)
 854 {
 855         u32 reg = 0;
 856         /* Enable QuadSPI clock */
 857         switch (qspi_num) {
 858         case 0:
 859                 /* disable the clock gate */
 860                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 861
 862                 /* set 50M  : (50 = 396 / 2 / 4) */
 863                 reg = readl(&imx_ccm->cscmr1);
 864                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 865                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 866                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 867                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 868                 writel(reg, &imx_ccm->cscmr1);
 869
 870                 /* enable the clock gate */
 871                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 872                 break;
 873         case 1:
 874                 /*
 875                  * disable the clock gate
 876                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 877                  * disable both of them.
 878                  */
 879                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 880                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 881
 882                 /* set 50M  : (50 = 396 / 2 / 4) */
 883                 reg = readl(&imx_ccm->cs2cdr);
 884                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 885                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 886                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 887                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 888                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 889                 writel(reg, &imx_ccm->cs2cdr);
 890
 891                 /*enable the clock gate*/
 892                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 893                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 894                 break;
 895         default:
 896                 break;
 897         }
 898 }
 899 #endif
 900
 901 #ifdef CONFIG_FEC_MXC
 902 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 903 {
 904         u32 reg = 0;
 905         s32 timeout = 100000;
 906
 907         struct anatop_regs __iomem *anatop =
 908                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 909
 910         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 911                 return -EINVAL;
 912
 913         reg = readl(&anatop->pll_enet);
 914
 915         if (fec_id == 0) {
 916                 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 917                 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 918         } else if (fec_id == 1) {
 919                 /* Only i.MX6SX/UL support ENET2 */
 920                 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
 921                         return -EINVAL;
 922                 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 923                 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
 924         } else {
 925                 return -EINVAL;
 926         }
 927
 928         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 929             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 930                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 931                 writel(reg, &anatop->pll_enet);
 932                 while (timeout--) {
 933                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 934                                 break;
 935                 }
 936                 if (timeout < 0)
 937                         return -ETIMEDOUT;
 938         }
 939
 940         /* Enable FEC clock */
 941         if (fec_id == 0)
 942                 reg |= BM_ANADIG_PLL_ENET_ENABLE;
 943         else
 944                 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 945         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 946         writel(reg, &anatop->pll_enet);
 947
 948 #ifdef CONFIG_MX6SX
 949         /* Disable enet system clcok before switching clock parent */
 950         reg = readl(&imx_ccm->CCGR3);
 951         reg &= ~MXC_CCM_CCGR3_ENET_MASK;
 952         writel(reg, &imx_ccm->CCGR3);
 953
 954         /*
 955          * Set enet ahb clock to 200MHz
 956          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 957          */
 958         reg = readl(&imx_ccm->chsccdr);
 959         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 960                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 961                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 962         /* PLL2 PFD2 */
 963         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 964         /* Div = 2*/
 965         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 966         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 967         writel(reg, &imx_ccm->chsccdr);
 968
 969         /* Enable enet system clock */
 970         reg = readl(&imx_ccm->CCGR3);
 971         reg |= MXC_CCM_CCGR3_ENET_MASK;
 972         writel(reg, &imx_ccm->CCGR3);
 973 #endif
 974         return 0;
 975 }
 976 #endif
 977
 978 static u32 get_usdhc_clk(u32 port)
 979 {
 980         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 981         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 982         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 983
 984         switch (port) {
 985         case 0:
 986                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 987                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 988                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 989
 990                 break;
 991         case 1:
 992                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 993                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 994                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 995
 996                 break;
 997         case 2:
 998                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 999                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
1000                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
1001
1002                 break;
1003         case 3:
1004                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
1005                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
1006                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
1007
1008                 break;
1009         default:
1010                 break;
1011         }
1012
1013         if (clk_sel)
1014                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
1015         else
1016                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
1017
1018         return root_freq / (usdhc_podf + 1);
1019 }
1020
1021 u32 imx_get_uartclk(void)
1022 {
1023         return get_uart_clk();
1024 }
1025
1026 u32 imx_get_fecclk(void)
1027 {
1028         return mxc_get_clock(MXC_IPG_CLK);
1029 }
1030
1031 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
1032 static int enable_enet_pll(uint32_t en)
1033 {
1034         struct mxc_ccm_reg *const imx_ccm
1035                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
1036         s32 timeout = 100000;
1037         u32 reg = 0;
1038
1039         /* Enable PLLs */
1040         reg = readl(&imx_ccm->analog_pll_enet);
1041         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
1042         writel(reg, &imx_ccm->analog_pll_enet);
1043         reg |= BM_ANADIG_PLL_SYS_ENABLE;
1044         while (timeout--) {
1045                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
1046                         break;
1047         }
1048         if (timeout <= 0)
1049                 return -EIO;
1050         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
1051         writel(reg, &imx_ccm->analog_pll_enet);
1052         reg |= en;
1053         writel(reg, &imx_ccm->analog_pll_enet);
1054         return 0;
1055 }
1056 #endif
1057
1058 #ifdef CONFIG_CMD_SATA
1059 static void ungate_sata_clock(void)
1060 {
1061         struct mxc_ccm_reg *const imx_ccm =
1062                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1063
1064         /* Enable SATA clock. */
1065         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1066 }
1067
1068 int enable_sata_clock(void)
1069 {
1070         ungate_sata_clock();
1071         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1072 }
1073
1074 void disable_sata_clock(void)
1075 {
1076         struct mxc_ccm_reg *const imx_ccm =
1077                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1078
1079         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1080 }
1081 #endif
1082
1083 #ifdef CONFIG_PCIE_IMX
1084 static void ungate_pcie_clock(void)
1085 {
1086         struct mxc_ccm_reg *const imx_ccm =
1087                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1088
1089         /* Enable PCIe clock. */
1090         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1091 }
1092
1093 int enable_pcie_clock(void)
1094 {
1095         struct anatop_regs *anatop_regs =
1096                 (struct anatop_regs *)ANATOP_BASE_ADDR;
1097         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1098         u32 lvds1_clk_sel;
1099
1100         /*
1101          * Here be dragons!
1102          *
1103          * The register ANATOP_MISC1 is not documented in the Freescale
1104          * MX6RM. The register that is mapped in the ANATOP space and
1105          * marked as ANATOP_MISC1 is actually documented in the PMU section
1106          * of the datasheet as PMU_MISC1.
1107          *
1108          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1109          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1110          * for PCI express link that is clocked from the i.MX6.
1111          */
1112 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
1113 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
1114 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
1115 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1116 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1117
1118         if (is_mx6sx())
1119                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1120         else
1121                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1122
1123         clrsetbits_le32(&anatop_regs->ana_misc1,
1124                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1125                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1126                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1127
1128         /* PCIe reference clock sourced from AXI. */
1129         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1130
1131         /* Party time! Ungate the clock to the PCIe. */
1132 #ifdef CONFIG_CMD_SATA
1133         ungate_sata_clock();
1134 #endif
1135         ungate_pcie_clock();
1136
1137         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1138                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1139 }
1140 #endif
1141
1142 #ifdef CONFIG_SECURE_BOOT
1143 void hab_caam_clock_enable(unsigned char enable)
1144 {
1145         u32 reg;
1146
1147         if (is_mx6ull()) {
1148                 /* CG5, DCP clock */
1149                 reg = __raw_readl(&imx_ccm->CCGR0);
1150                 if (enable)
1151                         reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
1152                 else
1153                         reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
1154                 __raw_writel(reg, &imx_ccm->CCGR0);
1155         } else {
1156                 /* CG4 ~ CG6, CAAM clocks */
1157                 reg = __raw_readl(&imx_ccm->CCGR0);
1158                 if (enable)
1159                         reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1160                                 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1161                                 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1162                 else
1163                         reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1164                                 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1165                                 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1166                 __raw_writel(reg, &imx_ccm->CCGR0);
1167         }
1168
1169         /* EMI slow clk */
1170         reg = __raw_readl(&imx_ccm->CCGR6);
1171         if (enable)
1172                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1173         else
1174                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1175         __raw_writel(reg, &imx_ccm->CCGR6);
1176 }
1177 #endif
1178
1179 static void enable_pll3(void)
1180 {
1181         struct anatop_regs __iomem *anatop =
1182                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1183
1184         /* make sure pll3 is enabled */
1185         if ((readl(&anatop->usb1_pll_480_ctrl) &
1186                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1187                 /* enable pll's power */
1188                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1189                        &anatop->usb1_pll_480_ctrl_set);
1190                 writel(0x80, &anatop->ana_misc2_clr);
1191                 /* wait for pll lock */
1192                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1193                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1194                         ;
1195                 /* disable bypass */
1196                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1197                        &anatop->usb1_pll_480_ctrl_clr);
1198                 /* enable pll output */
1199                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1200                        &anatop->usb1_pll_480_ctrl_set);
1201         }
1202 }
1203
1204 void enable_thermal_clk(void)
1205 {
1206         enable_pll3();
1207 }
1208
1209 unsigned int mxc_get_clock(enum mxc_clock clk)
1210 {
1211         switch (clk) {
1212         case MXC_ARM_CLK:
1213                 return get_mcu_main_clk();
1214         case MXC_PER_CLK:
1215                 return get_periph_clk();
1216         case MXC_AHB_CLK:
1217                 return get_ahb_clk();
1218         case MXC_IPG_CLK:
1219                 return get_ipg_clk();
1220         case MXC_IPG_PERCLK:
1221         case MXC_I2C_CLK:
1222                 return get_ipg_per_clk();
1223         case MXC_UART_CLK:
1224                 return get_uart_clk();
1225         case MXC_CSPI_CLK:
1226                 return get_cspi_clk();
1227         case MXC_AXI_CLK:
1228                 return get_axi_clk();
1229         case MXC_EMI_SLOW_CLK:
1230                 return get_emi_slow_clk();
1231         case MXC_DDR_CLK:
1232                 return get_mmdc_ch0_clk();
1233         case MXC_ESDHC_CLK:
1234                 return get_usdhc_clk(0);
1235         case MXC_ESDHC2_CLK:
1236                 return get_usdhc_clk(1);
1237         case MXC_ESDHC3_CLK:
1238                 return get_usdhc_clk(2);
1239         case MXC_ESDHC4_CLK:
1240                 return get_usdhc_clk(3);
1241         case MXC_SATA_CLK:
1242                 return get_ahb_clk();
1243         default:
1244                 printf("Unsupported MXC CLK: %d\n", clk);
1245                 break;
1246         }
1247
1248         return 0;
1249 }
1250
1251 /*
1252  * Dump some core clockes.
1253  */
1254 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1255 {
1256         u32 freq;
1257         freq = decode_pll(PLL_SYS, MXC_HCLK);
1258         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1259         freq = decode_pll(PLL_BUS, MXC_HCLK);
1260         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
1261         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1262         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
1263         freq = decode_pll(PLL_ENET, MXC_HCLK);
1264         printf("PLL_NET    %8d MHz\n", freq / 1000000);
1265
1266         printf("\n");
1267         printf("ARM        %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
1268         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1269         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1270 #ifdef CONFIG_MXC_SPI
1271         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1272 #endif
1273         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1274         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1275         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1276         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1277         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1278         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1279         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1280         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1281         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1282
1283         return 0;
1284 }
1285
1286 #ifndef CONFIG_MX6SX
1287 void enable_ipu_clock(void)
1288 {
1289         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1290         int reg;
1291         reg = readl(&mxc_ccm->CCGR3);
1292         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1293         writel(reg, &mxc_ccm->CCGR3);
1294
1295         if (is_mx6dqp()) {
1296                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1297                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1298         }
1299 }
1300 #endif
1301
1302 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1303         defined(CONFIG_MX6S)
1304 static void disable_ldb_di_clock_sources(void)
1305 {
1306         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1307         int reg;
1308
1309         /* Make sure PFDs are disabled at boot. */
1310         reg = readl(&mxc_ccm->analog_pfd_528);
1311         /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1312         if (is_mx6sdl())
1313                 reg |= 0x80008080;
1314         else
1315                 reg |= 0x80808080;
1316         writel(reg, &mxc_ccm->analog_pfd_528);
1317
1318         /* Disable PLL3 PFDs */
1319         reg = readl(&mxc_ccm->analog_pfd_480);
1320         reg |= 0x80808080;
1321         writel(reg, &mxc_ccm->analog_pfd_480);
1322
1323         /* Disable PLL5 */
1324         reg = readl(&mxc_ccm->analog_pll_video);
1325         reg &= ~(1 << 13);
1326         writel(reg, &mxc_ccm->analog_pll_video);
1327 }
1328
1329 static void enable_ldb_di_clock_sources(void)
1330 {
1331         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1332         int reg;
1333
1334         reg = readl(&mxc_ccm->analog_pfd_528);
1335         if (is_mx6sdl())
1336                 reg &= ~(0x80008080);
1337         else
1338                 reg &= ~(0x80808080);
1339         writel(reg, &mxc_ccm->analog_pfd_528);
1340
1341         reg = readl(&mxc_ccm->analog_pfd_480);
1342         reg &= ~(0x80808080);
1343         writel(reg, &mxc_ccm->analog_pfd_480);
1344 }
1345
1346 /*
1347  * Try call this function as early in the boot process as possible since the
1348  * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1349  */
1350 void select_ldb_di_clock_source(enum ldb_di_clock clk)
1351 {
1352         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1353         int reg;
1354
1355         /*
1356          * Need to follow a strict procedure when changing the LDB
1357          * clock, else we can introduce a glitch. Things to keep in
1358          * mind:
1359          * 1. The current and new parent clocks must be disabled.
1360          * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1361          * no CG bit.
1362          * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1363          * the top four options are in one mux and the PLL3 option along
1364          * with another option is in the second mux. There is third mux
1365          * used to decide between the first and second mux.
1366          * The code below switches the parent to the bottom mux first
1367          * and then manipulates the top mux. This ensures that no glitch
1368          * will enter the divider.
1369          *
1370          * Need to disable MMDC_CH1 clock manually as there is no CG bit
1371          * for this clock. The only way to disable this clock is to move
1372          * it to pll3_sw_clk and then to disable pll3_sw_clk
1373          * Make sure periph2_clk2_sel is set to pll3_sw_clk
1374          */
1375
1376         /* Disable all ldb_di clock parents */
1377         disable_ldb_di_clock_sources();
1378
1379         /* Set MMDC_CH1 mask bit */
1380         reg = readl(&mxc_ccm->ccdr);
1381         reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1382         writel(reg, &mxc_ccm->ccdr);
1383
1384         /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1385         reg = readl(&mxc_ccm->cbcmr);
1386         reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
1387         writel(reg, &mxc_ccm->cbcmr);
1388
1389         /*
1390          * Set the periph2_clk_sel to the top mux so that
1391          * mmdc_ch1 is from pll3_sw_clk.
1392          */
1393         reg = readl(&mxc_ccm->cbcdr);
1394         reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1395         writel(reg, &mxc_ccm->cbcdr);
1396
1397         /* Wait for the clock switch */
1398         while (readl(&mxc_ccm->cdhipr))
1399                 ;
1400         /* Disable pll3_sw_clk by selecting bypass clock source */
1401         reg = readl(&mxc_ccm->ccsr);
1402         reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1403         writel(reg, &mxc_ccm->ccsr);
1404
1405         /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1406         reg = readl(&mxc_ccm->cs2cdr);
1407         reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1408               | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1409         writel(reg, &mxc_ccm->cs2cdr);
1410
1411         /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1412         reg = readl(&mxc_ccm->cs2cdr);
1413         reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1414               | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1415         reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1416               | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1417         writel(reg, &mxc_ccm->cs2cdr);
1418
1419         /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1420         reg = readl(&mxc_ccm->cs2cdr);
1421         reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1422               | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1423         reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1424               | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1425         writel(reg, &mxc_ccm->cs2cdr);
1426
1427         /* Unbypass pll3_sw_clk */
1428         reg = readl(&mxc_ccm->ccsr);
1429         reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1430         writel(reg, &mxc_ccm->ccsr);
1431
1432         /*
1433          * Set the periph2_clk_sel back to the bottom mux so that
1434          * mmdc_ch1 is from its original parent.
1435          */
1436         reg = readl(&mxc_ccm->cbcdr);
1437         reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1438         writel(reg, &mxc_ccm->cbcdr);
1439
1440         /* Wait for the clock switch */
1441         while (readl(&mxc_ccm->cdhipr))
1442                 ;
1443         /* Clear MMDC_CH1 mask bit */
1444         reg = readl(&mxc_ccm->ccdr);
1445         reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1446         writel(reg, &mxc_ccm->ccdr);
1447
1448         enable_ldb_di_clock_sources();
1449 }
1450 #endif
1451
1452 #ifndef CONFIG_SYS_NO_FLASH
1453 void enable_eim_clk(unsigned char enable)
1454 {
1455         u32 reg;
1456
1457         reg = __raw_readl(&imx_ccm->CCGR6);
1458         if (enable)
1459                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1460         else
1461                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1462         __raw_writel(reg, &imx_ccm->CCGR6);
1463 }
1464 #endif
1465
1466 /***************************************************/
1467
1468 U_BOOT_CMD(
1469         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1470         "display clocks",
1471         ""
1472 );