git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_SYS,        /* System PLL */
  18         PLL_BUS,        /* System Bus PLL*/
  19         PLL_USBOTG,     /* OTG USB PLL */
  20         PLL_ENET,       /* ENET PLL */
  21         PLL_AUDIO,      /* AUDIO PLL */
  22         PLL_VIDEO,      /* AUDIO PLL */
  23 };
  24
  25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  26
  27 #ifdef CONFIG_MXC_OCOTP
  28 void enable_ocotp_clk(unsigned char enable)
  29 {
  30         u32 reg;
  31
  32         reg = __raw_readl(&imx_ccm->CCGR2);
  33         if (enable)
  34                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  35         else
  36                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  37         __raw_writel(reg, &imx_ccm->CCGR2);
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_NAND_MXS
  42 void setup_gpmi_io_clk(u32 cfg)
  43 {
  44         /* Disable clocks per ERR007177 from MX6 errata */
  45         clrbits_le32(&imx_ccm->CCGR4,
  46                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  47                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  48                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  49                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  50                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  51
  52 #if defined(CONFIG_MX6SX)
  53         clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  54
  55         clrsetbits_le32(&imx_ccm->cs2cdr,
  56                         MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  57                         MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  58                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  59                         cfg);
  60
  61         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  62 #else
  63         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  64
  65         clrsetbits_le32(&imx_ccm->cs2cdr,
  66                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  67                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  68                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  69                         cfg);
  70
  71         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  72 #endif
  73         setbits_le32(&imx_ccm->CCGR4,
  74                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  77                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  78                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  79 }
  80 #endif
  81
  82 void enable_usboh3_clk(unsigned char enable)
  83 {
  84         u32 reg;
  85
  86         reg = __raw_readl(&imx_ccm->CCGR6);
  87         if (enable)
  88                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  89         else
  90                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  91         __raw_writel(reg, &imx_ccm->CCGR6);
  92
  93 }
  94
  95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  96 void enable_enet_clk(unsigned char enable)
  97 {
  98         u32 mask, *addr;
  99
 100         if (is_mx6ull()) {
 101                 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
 102                 addr = &imx_ccm->CCGR0;
 103         } else if (is_mx6ul()) {
 104                 mask = MXC_CCM_CCGR3_ENET_MASK;
 105                 addr = &imx_ccm->CCGR3;
 106         } else {
 107                 mask = MXC_CCM_CCGR1_ENET_MASK;
 108                 addr = &imx_ccm->CCGR1;
 109         }
 110
 111         if (enable)
 112                 setbits_le32(addr, mask);
 113         else
 114                 clrbits_le32(addr, mask);
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_MXC_UART
 119 void enable_uart_clk(unsigned char enable)
 120 {
 121         u32 mask;
 122
 123         if (is_mx6ul() || is_mx6ull())
 124                 mask = MXC_CCM_CCGR5_UART_MASK;
 125         else
 126                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 127
 128         if (enable)
 129                 setbits_le32(&imx_ccm->CCGR5, mask);
 130         else
 131                 clrbits_le32(&imx_ccm->CCGR5, mask);
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_MMC
 136 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 137 {
 138         u32 mask;
 139
 140         if (bus_num > 3)
 141                 return -EINVAL;
 142
 143         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 144         if (enable)
 145                 setbits_le32(&imx_ccm->CCGR6, mask);
 146         else
 147                 clrbits_le32(&imx_ccm->CCGR6, mask);
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_SYS_I2C_MXC
 154 /* i2c_num can be from 0 - 3 */
 155 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 156 {
 157         u32 reg;
 158         u32 mask;
 159         u32 *addr;
 160
 161         if (i2c_num > 3)
 162                 return -EINVAL;
 163         if (i2c_num < 3) {
 164                 mask = MXC_CCM_CCGR_CG_MASK
 165                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 166                         + (i2c_num << 1));
 167                 reg = __raw_readl(&imx_ccm->CCGR2);
 168                 if (enable)
 169                         reg |= mask;
 170                 else
 171                         reg &= ~mask;
 172                 __raw_writel(reg, &imx_ccm->CCGR2);
 173         } else {
 174                 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
 175                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 176                         addr = &imx_ccm->CCGR6;
 177                 } else {
 178                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 179                         addr = &imx_ccm->CCGR1;
 180                 }
 181                 reg = __raw_readl(addr);
 182                 if (enable)
 183                         reg |= mask;
 184                 else
 185                         reg &= ~mask;
 186                 __raw_writel(reg, addr);
 187         }
 188         return 0;
 189 }
 190 #endif
 191
 192 /* spi_num can be from 0 - SPI_MAX_NUM */
 193 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 194 {
 195         u32 reg;
 196         u32 mask;
 197
 198         if (spi_num > SPI_MAX_NUM)
 199                 return -EINVAL;
 200
 201         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 202         reg = __raw_readl(&imx_ccm->CCGR1);
 203         if (enable)
 204                 reg |= mask;
 205         else
 206                 reg &= ~mask;
 207         __raw_writel(reg, &imx_ccm->CCGR1);
 208         return 0;
 209 }
 210 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 211 {
 212         u32 div, test_div, pll_num, pll_denom;
 213
 214         switch (pll) {
 215         case PLL_SYS:
 216                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 217                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 218
 219                 return (infreq * div) >> 1;
 220         case PLL_BUS:
 221                 div = __raw_readl(&imx_ccm->analog_pll_528);
 222                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 223
 224                 return infreq * (20 + (div << 1));
 225         case PLL_USBOTG:
 226                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 227                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 228
 229                 return infreq * (20 + (div << 1));
 230         case PLL_ENET:
 231                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 232                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 233
 234                 return 25000000 * (div + (div >> 1) + 1);
 235         case PLL_AUDIO:
 236                 div = __raw_readl(&imx_ccm->analog_pll_audio);
 237                 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
 238                         return 0;
 239                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 240                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 241                         return MXC_HCLK;
 242                 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
 243                 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
 244                 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
 245                         BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
 246                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 247                 if (test_div == 3) {
 248                         debug("Error test_div\n");
 249                         return 0;
 250                 }
 251                 test_div = 1 << (2 - test_div);
 252
 253                 return infreq * (div + pll_num / pll_denom) / test_div;
 254         case PLL_VIDEO:
 255                 div = __raw_readl(&imx_ccm->analog_pll_video);
 256                 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
 257                         return 0;
 258                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 259                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 260                         return MXC_HCLK;
 261                 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
 262                 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
 263                 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 264                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 265                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 266                 if (test_div == 3) {
 267                         debug("Error test_div\n");
 268                         return 0;
 269                 }
 270                 test_div = 1 << (2 - test_div);
 271
 272                 return infreq * (div + pll_num / pll_denom) / test_div;
 273         default:
 274                 return 0;
 275         }
 276         /* NOTREACHED */
 277 }
 278 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 279 {
 280         u32 div;
 281         u64 freq;
 282
 283         switch (pll) {
 284         case PLL_BUS:
 285                 if (!is_mx6ul() && !is_mx6ull()) {
 286                         if (pfd_num == 3) {
 287                                 /* No PFD3 on PLL2 */
 288                                 return 0;
 289                         }
 290                 }
 291                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 292                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 293                 break;
 294         case PLL_USBOTG:
 295                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 296                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 297                 break;
 298         default:
 299                 /* No PFD on other PLL                                       */
 300                 return 0;
 301         }
 302
 303         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 304                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 305 }
 306
 307 static u32 get_mcu_main_clk(void)
 308 {
 309         u32 reg, freq;
 310
 311         reg = __raw_readl(&imx_ccm->cacrr);
 312         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 313         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 314         freq = decode_pll(PLL_SYS, MXC_HCLK);
 315
 316         return freq / (reg + 1);
 317 }
 318
 319 u32 get_periph_clk(void)
 320 {
 321         u32 reg, div = 0, freq = 0;
 322
 323         reg = __raw_readl(&imx_ccm->cbcdr);
 324         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 325                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 326                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 327                 reg = __raw_readl(&imx_ccm->cbcmr);
 328                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 329                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 330
 331                 switch (reg) {
 332                 case 0:
 333                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 334                         break;
 335                 case 1:
 336                 case 2:
 337                         freq = MXC_HCLK;
 338                         break;
 339                 default:
 340                         break;
 341                 }
 342         } else {
 343                 reg = __raw_readl(&imx_ccm->cbcmr);
 344                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 345                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 346
 347                 switch (reg) {
 348                 case 0:
 349                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 350                         break;
 351                 case 1:
 352                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 353                         break;
 354                 case 2:
 355                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 356                         break;
 357                 case 3:
 358                         /* static / 2 divider */
 359                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 360                         break;
 361                 default:
 362                         break;
 363                 }
 364         }
 365
 366         return freq / (div + 1);
 367 }
 368
 369 static u32 get_ipg_clk(void)
 370 {
 371         u32 reg, ipg_podf;
 372
 373         reg = __raw_readl(&imx_ccm->cbcdr);
 374         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 375         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 376
 377         return get_ahb_clk() / (ipg_podf + 1);
 378 }
 379
 380 static u32 get_ipg_per_clk(void)
 381 {
 382         u32 reg, perclk_podf;
 383
 384         reg = __raw_readl(&imx_ccm->cscmr1);
 385         if (is_mx6sl() || is_mx6sx() ||
 386             is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
 387                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 388                         return MXC_HCLK; /* OSC 24Mhz */
 389         }
 390
 391         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 392
 393         return get_ipg_clk() / (perclk_podf + 1);
 394 }
 395
 396 static u32 get_uart_clk(void)
 397 {
 398         u32 reg, uart_podf;
 399         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 400         reg = __raw_readl(&imx_ccm->cscdr1);
 401
 402         if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
 403             is_mx6ull()) {
 404                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 405                         freq = MXC_HCLK;
 406         }
 407
 408         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 409         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 410
 411         return freq / (uart_podf + 1);
 412 }
 413
 414 static u32 get_cspi_clk(void)
 415 {
 416         u32 reg, cspi_podf;
 417
 418         reg = __raw_readl(&imx_ccm->cscdr2);
 419         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 420                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 421
 422         if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
 423             is_mx6ull()) {
 424                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 425                         return MXC_HCLK / (cspi_podf + 1);
 426         }
 427
 428         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 429 }
 430
 431 static u32 get_axi_clk(void)
 432 {
 433         u32 root_freq, axi_podf;
 434         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 435
 436         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 437         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 438
 439         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 440                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 441                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 442                 else
 443                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 444         } else
 445                 root_freq = get_periph_clk();
 446
 447         return  root_freq / (axi_podf + 1);
 448 }
 449
 450 static u32 get_emi_slow_clk(void)
 451 {
 452         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 453
 454         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 455         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 456         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 457         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 458         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 459
 460         switch (emi_clk_sel) {
 461         case 0:
 462                 root_freq = get_axi_clk();
 463                 break;
 464         case 1:
 465                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 466                 break;
 467         case 2:
 468                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 469                 break;
 470         case 3:
 471                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 472                 break;
 473         }
 474
 475         return root_freq / (emi_slow_podf + 1);
 476 }
 477
 478 static u32 get_mmdc_ch0_clk(void)
 479 {
 480         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 481         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 482
 483         u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 484
 485         if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
 486                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 487                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 488                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 489                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 490                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 491                         if (is_mx6sl()) {
 492                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 493                                         freq = MXC_HCLK;
 494                                 else
 495                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 496                         } else {
 497                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 498                                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 499                                 else
 500                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 501                         }
 502                 } else {
 503                         per2_clk2_podf = 0;
 504                         switch ((cbcmr &
 505                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 506                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 507                         case 0:
 508                                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 509                                 break;
 510                         case 1:
 511                                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 512                                 break;
 513                         case 2:
 514                                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 515                                 break;
 516                         case 3:
 517                                 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
 518                                 switch (pmu_misc2_audio_div) {
 519                                 case 0:
 520                                 case 2:
 521                                         pmu_misc2_audio_div = 1;
 522                                         break;
 523                                 case 1:
 524                                         pmu_misc2_audio_div = 2;
 525                                         break;
 526                                 case 3:
 527                                         pmu_misc2_audio_div = 4;
 528                                         break;
 529                                 }
 530                                 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
 531                                         pmu_misc2_audio_div;
 532                                 break;
 533                         }
 534                 }
 535                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 536         } else {
 537                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 538                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 539                 return get_periph_clk() / (podf + 1);
 540         }
 541 }
 542
 543 #if defined(CONFIG_VIDEO_MXS)
 544 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
 545                             u32 post_div)
 546 {
 547         u32 reg = 0;
 548         ulong start;
 549
 550         debug("pll5 div = %d, num = %d, denom = %d\n",
 551               pll_div, pll_num, pll_denom);
 552
 553         /* Power up PLL5 video */
 554         writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
 555                BM_ANADIG_PLL_VIDEO_BYPASS |
 556                BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 557                BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 558                &imx_ccm->analog_pll_video_clr);
 559
 560         /* Set div, num and denom */
 561         switch (post_div) {
 562         case 1:
 563                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 564                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
 565                        &imx_ccm->analog_pll_video_set);
 566                 break;
 567         case 2:
 568                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 569                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
 570                        &imx_ccm->analog_pll_video_set);
 571                 break;
 572         case 4:
 573                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 574                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
 575                        &imx_ccm->analog_pll_video_set);
 576                 break;
 577         default:
 578                 puts("Wrong test_div!\n");
 579                 return -EINVAL;
 580         }
 581
 582         writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
 583                &imx_ccm->analog_pll_video_num);
 584         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
 585                &imx_ccm->analog_pll_video_denom);
 586
 587         /* Wait PLL5 lock */
 588         start = get_timer(0);   /* Get current timestamp */
 589
 590         do {
 591                 reg = readl(&imx_ccm->analog_pll_video);
 592                 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
 593                         /* Enable PLL out */
 594                         writel(BM_ANADIG_PLL_VIDEO_ENABLE,
 595                                &imx_ccm->analog_pll_video_set);
 596                         return 0;
 597                 }
 598         } while (get_timer(0) < (start + 10)); /* Wait 10ms */
 599
 600         puts("Lock PLL5 timeout\n");
 601
 602         return -ETIME;
 603 }
 604
 605 /*
 606  * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
 607  *
 608  * 'freq' using KHz as unit, see driver/video/mxsfb.c.
 609  */
 610 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 611 {
 612         u32 reg = 0;
 613         u32 hck = MXC_HCLK / 1000;
 614         /* DIV_SELECT ranges from 27 to 54 */
 615         u32 min = hck * 27;
 616         u32 max = hck * 54;
 617         u32 temp, best = 0;
 618         u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
 619         u32 pll_div, pll_num, pll_denom, post_div = 1;
 620
 621         debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 622
 623         if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
 624                 debug("This chip not support lcd!\n");
 625                 return;
 626         }
 627
 628         if (base_addr == LCDIF1_BASE_ADDR) {
 629                 reg = readl(&imx_ccm->cscdr2);
 630                 /* Can't change clocks when clock not from pre-mux */
 631                 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
 632                         return;
 633         }
 634
 635         if (is_mx6sx()) {
 636                 reg = readl(&imx_ccm->cscdr2);
 637                 /* Can't change clocks when clock not from pre-mux */
 638                 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
 639                         return;
 640         }
 641
 642         temp = freq * max_pred * max_postd;
 643         if (temp < min) {
 644                 /*
 645                  * Register: PLL_VIDEO
 646                  * Bit Field: POST_DIV_SELECT
 647                  * 00 — Divide by 4.
 648                  * 01 — Divide by 2.
 649                  * 10 — Divide by 1.
 650                  * 11 — Reserved
 651                  * No need to check post_div(1)
 652                  */
 653                 for (post_div = 2; post_div <= 4; post_div <<= 1) {
 654                         if ((temp * post_div) > min) {
 655                                 freq *= post_div;
 656                                 break;
 657                         }
 658                 }
 659
 660                 if (post_div > 4) {
 661                         printf("Fail to set rate to %dkhz", freq);
 662                         return;
 663                 }
 664         }
 665
 666         /* Choose the best pred and postd to match freq for lcd */
 667         for (i = 1; i <= max_pred; i++) {
 668                 for (j = 1; j <= max_postd; j++) {
 669                         temp = freq * i * j;
 670                         if (temp > max || temp < min)
 671                                 continue;
 672                         if (best == 0 || temp < best) {
 673                                 best = temp;
 674                                 pred = i;
 675                                 postd = j;
 676                         }
 677                 }
 678         }
 679
 680         if (best == 0) {
 681                 printf("Fail to set rate to %dKHz", freq);
 682                 return;
 683         }
 684
 685         debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
 686
 687         pll_div = best / hck;
 688         pll_denom = 1000000;
 689         pll_num = (best - hck * pll_div) * pll_denom / hck;
 690
 691         /*
 692          *                                  pll_num
 693          *             (24MHz * (pll_div + --------- ))
 694          *                                 pll_denom
 695          *freq KHz =  --------------------------------
 696          *             post_div * pred * postd * 1000
 697          */
 698
 699         if (base_addr == LCDIF1_BASE_ADDR) {
 700                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 701                         return;
 702
 703                 /* Select pre-lcd clock to PLL5 and set pre divider */
 704                 clrsetbits_le32(&imx_ccm->cscdr2,
 705                                 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
 706                                 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
 707                                 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
 708                                 ((pred - 1) <<
 709                                  MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
 710
 711                 /* Set the post divider */
 712                 clrsetbits_le32(&imx_ccm->cbcmr,
 713                                 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 714                                 ((postd - 1) <<
 715                                  MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
 716         } else if (is_mx6sx()) {
 717                 /* Setting LCDIF2 for i.MX6SX */
 718                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 719                         return;
 720
 721                 /* Select pre-lcd clock to PLL5 and set pre divider */
 722                 clrsetbits_le32(&imx_ccm->cscdr2,
 723                                 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
 724                                 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
 725                                 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
 726                                 ((pred - 1) <<
 727                                  MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
 728
 729                 /* Set the post divider */
 730                 clrsetbits_le32(&imx_ccm->cscmr1,
 731                                 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
 732                                 ((postd - 1) <<
 733                                  MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 734         }
 735 }
 736
 737 int enable_lcdif_clock(u32 base_addr)
 738 {
 739         u32 reg = 0;
 740         u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 741
 742         if (is_mx6sx()) {
 743                 if ((base_addr != LCDIF1_BASE_ADDR) &&
 744                     (base_addr != LCDIF2_BASE_ADDR)) {
 745                         puts("Wrong LCD interface!\n");
 746                         return -EINVAL;
 747                 }
 748                 /* Set to pre-mux clock at default */
 749                 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 750                         MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
 751                         MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 752                 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 753                         (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
 754                          MXC_CCM_CCGR3_DISP_AXI_MASK) :
 755                         (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 756                          MXC_CCM_CCGR3_DISP_AXI_MASK);
 757         } else if (is_mx6ul() || is_mx6ull()) {
 758                 if (base_addr != LCDIF1_BASE_ADDR) {
 759                         puts("Wrong LCD interface!\n");
 760                         return -EINVAL;
 761                 }
 762                 /* Set to pre-mux clock at default */
 763                 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 764                 lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
 765         } else {
 766                 return 0;
 767         }
 768
 769         reg = readl(&imx_ccm->cscdr2);
 770         reg &= ~lcdif_clk_sel_mask;
 771         writel(reg, &imx_ccm->cscdr2);
 772
 773         /* Enable the LCDIF pix clock */
 774         reg = readl(&imx_ccm->CCGR3);
 775         reg |= lcdif_ccgr3_mask;
 776         writel(reg, &imx_ccm->CCGR3);
 777
 778         reg = readl(&imx_ccm->CCGR2);
 779         reg |= MXC_CCM_CCGR2_LCD_MASK;
 780         writel(reg, &imx_ccm->CCGR2);
 781
 782         return 0;
 783 }
 784 #endif
 785
 786 #ifdef CONFIG_FSL_QSPI
 787 /* qspi_num can be from 0 - 1 */
 788 void enable_qspi_clk(int qspi_num)
 789 {
 790         u32 reg = 0;
 791         /* Enable QuadSPI clock */
 792         switch (qspi_num) {
 793         case 0:
 794                 /* disable the clock gate */
 795                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 796
 797                 /* set 50M  : (50 = 396 / 2 / 4) */
 798                 reg = readl(&imx_ccm->cscmr1);
 799                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 800                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 801                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 802                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 803                 writel(reg, &imx_ccm->cscmr1);
 804
 805                 /* enable the clock gate */
 806                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 807                 break;
 808         case 1:
 809                 /*
 810                  * disable the clock gate
 811                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 812                  * disable both of them.
 813                  */
 814                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 815                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 816
 817                 /* set 50M  : (50 = 396 / 2 / 4) */
 818                 reg = readl(&imx_ccm->cs2cdr);
 819                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 820                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 821                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 822                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 823                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 824                 writel(reg, &imx_ccm->cs2cdr);
 825
 826                 /*enable the clock gate*/
 827                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 828                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 829                 break;
 830         default:
 831                 break;
 832         }
 833 }
 834 #endif
 835
 836 #ifdef CONFIG_FEC_MXC
 837 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 838 {
 839         u32 reg = 0;
 840         s32 timeout = 100000;
 841
 842         struct anatop_regs __iomem *anatop =
 843                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 844
 845         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 846                 return -EINVAL;
 847
 848         reg = readl(&anatop->pll_enet);
 849
 850         if (fec_id == 0) {
 851                 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 852                 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 853         } else if (fec_id == 1) {
 854                 /* Only i.MX6SX/UL support ENET2 */
 855                 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
 856                         return -EINVAL;
 857                 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 858                 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
 859         } else {
 860                 return -EINVAL;
 861         }
 862
 863         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 864             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 865                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 866                 writel(reg, &anatop->pll_enet);
 867                 while (timeout--) {
 868                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 869                                 break;
 870                 }
 871                 if (timeout < 0)
 872                         return -ETIMEDOUT;
 873         }
 874
 875         /* Enable FEC clock */
 876         if (fec_id == 0)
 877                 reg |= BM_ANADIG_PLL_ENET_ENABLE;
 878         else
 879                 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 880         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 881         writel(reg, &anatop->pll_enet);
 882
 883 #ifdef CONFIG_MX6SX
 884         /*
 885          * Set enet ahb clock to 200MHz
 886          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 887          */
 888         reg = readl(&imx_ccm->chsccdr);
 889         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 890                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 891                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 892         /* PLL2 PFD2 */
 893         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 894         /* Div = 2*/
 895         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 896         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 897         writel(reg, &imx_ccm->chsccdr);
 898
 899         /* Enable enet system clock */
 900         reg = readl(&imx_ccm->CCGR3);
 901         reg |= MXC_CCM_CCGR3_ENET_MASK;
 902         writel(reg, &imx_ccm->CCGR3);
 903 #endif
 904         return 0;
 905 }
 906 #endif
 907
 908 static u32 get_usdhc_clk(u32 port)
 909 {
 910         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 911         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 912         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 913
 914         switch (port) {
 915         case 0:
 916                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 917                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 918                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 919
 920                 break;
 921         case 1:
 922                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 923                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 924                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 925
 926                 break;
 927         case 2:
 928                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 929                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 930                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 931
 932                 break;
 933         case 3:
 934                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 935                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 936                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 937
 938                 break;
 939         default:
 940                 break;
 941         }
 942
 943         if (clk_sel)
 944                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 945         else
 946                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 947
 948         return root_freq / (usdhc_podf + 1);
 949 }
 950
 951 u32 imx_get_uartclk(void)
 952 {
 953         return get_uart_clk();
 954 }
 955
 956 u32 imx_get_fecclk(void)
 957 {
 958         return mxc_get_clock(MXC_IPG_CLK);
 959 }
 960
 961 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 962 static int enable_enet_pll(uint32_t en)
 963 {
 964         struct mxc_ccm_reg *const imx_ccm
 965                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 966         s32 timeout = 100000;
 967         u32 reg = 0;
 968
 969         /* Enable PLLs */
 970         reg = readl(&imx_ccm->analog_pll_enet);
 971         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 972         writel(reg, &imx_ccm->analog_pll_enet);
 973         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 974         while (timeout--) {
 975                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 976                         break;
 977         }
 978         if (timeout <= 0)
 979                 return -EIO;
 980         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 981         writel(reg, &imx_ccm->analog_pll_enet);
 982         reg |= en;
 983         writel(reg, &imx_ccm->analog_pll_enet);
 984         return 0;
 985 }
 986 #endif
 987
 988 #ifdef CONFIG_CMD_SATA
 989 static void ungate_sata_clock(void)
 990 {
 991         struct mxc_ccm_reg *const imx_ccm =
 992                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 993
 994         /* Enable SATA clock. */
 995         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 996 }
 997
 998 int enable_sata_clock(void)
 999 {
1000         ungate_sata_clock();
1001         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1002 }
1003
1004 void disable_sata_clock(void)
1005 {
1006         struct mxc_ccm_reg *const imx_ccm =
1007                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1008
1009         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1010 }
1011 #endif
1012
1013 #ifdef CONFIG_PCIE_IMX
1014 static void ungate_pcie_clock(void)
1015 {
1016         struct mxc_ccm_reg *const imx_ccm =
1017                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1018
1019         /* Enable PCIe clock. */
1020         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1021 }
1022
1023 int enable_pcie_clock(void)
1024 {
1025         struct anatop_regs *anatop_regs =
1026                 (struct anatop_regs *)ANATOP_BASE_ADDR;
1027         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1028         u32 lvds1_clk_sel;
1029
1030         /*
1031          * Here be dragons!
1032          *
1033          * The register ANATOP_MISC1 is not documented in the Freescale
1034          * MX6RM. The register that is mapped in the ANATOP space and
1035          * marked as ANATOP_MISC1 is actually documented in the PMU section
1036          * of the datasheet as PMU_MISC1.
1037          *
1038          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1039          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1040          * for PCI express link that is clocked from the i.MX6.
1041          */
1042 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
1043 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
1044 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
1045 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1046 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1047
1048         if (is_mx6sx())
1049                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1050         else
1051                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1052
1053         clrsetbits_le32(&anatop_regs->ana_misc1,
1054                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1055                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1056                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1057
1058         /* PCIe reference clock sourced from AXI. */
1059         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1060
1061         /* Party time! Ungate the clock to the PCIe. */
1062 #ifdef CONFIG_CMD_SATA
1063         ungate_sata_clock();
1064 #endif
1065         ungate_pcie_clock();
1066
1067         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1068                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1069 }
1070 #endif
1071
1072 #ifdef CONFIG_SECURE_BOOT
1073 void hab_caam_clock_enable(unsigned char enable)
1074 {
1075         u32 reg;
1076
1077         if (is_mx6ull()) {
1078                 /* CG5, DCP clock */
1079                 reg = __raw_readl(&imx_ccm->CCGR0);
1080                 if (enable)
1081                         reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
1082                 else
1083                         reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
1084                 __raw_writel(reg, &imx_ccm->CCGR0);
1085         } else {
1086                 /* CG4 ~ CG6, CAAM clocks */
1087                 reg = __raw_readl(&imx_ccm->CCGR0);
1088                 if (enable)
1089                         reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1090                                 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1091                                 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1092                 else
1093                         reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1094                                 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1095                                 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1096                 __raw_writel(reg, &imx_ccm->CCGR0);
1097         }
1098
1099         /* EMI slow clk */
1100         reg = __raw_readl(&imx_ccm->CCGR6);
1101         if (enable)
1102                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1103         else
1104                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1105         __raw_writel(reg, &imx_ccm->CCGR6);
1106 }
1107 #endif
1108
1109 static void enable_pll3(void)
1110 {
1111         struct anatop_regs __iomem *anatop =
1112                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1113
1114         /* make sure pll3 is enabled */
1115         if ((readl(&anatop->usb1_pll_480_ctrl) &
1116                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1117                 /* enable pll's power */
1118                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1119                        &anatop->usb1_pll_480_ctrl_set);
1120                 writel(0x80, &anatop->ana_misc2_clr);
1121                 /* wait for pll lock */
1122                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1123                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1124                         ;
1125                 /* disable bypass */
1126                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1127                        &anatop->usb1_pll_480_ctrl_clr);
1128                 /* enable pll output */
1129                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1130                        &anatop->usb1_pll_480_ctrl_set);
1131         }
1132 }
1133
1134 void enable_thermal_clk(void)
1135 {
1136         enable_pll3();
1137 }
1138
1139 unsigned int mxc_get_clock(enum mxc_clock clk)
1140 {
1141         switch (clk) {
1142         case MXC_ARM_CLK:
1143                 return get_mcu_main_clk();
1144         case MXC_PER_CLK:
1145                 return get_periph_clk();
1146         case MXC_AHB_CLK:
1147                 return get_ahb_clk();
1148         case MXC_IPG_CLK:
1149                 return get_ipg_clk();
1150         case MXC_IPG_PERCLK:
1151         case MXC_I2C_CLK:
1152                 return get_ipg_per_clk();
1153         case MXC_UART_CLK:
1154                 return get_uart_clk();
1155         case MXC_CSPI_CLK:
1156                 return get_cspi_clk();
1157         case MXC_AXI_CLK:
1158                 return get_axi_clk();
1159         case MXC_EMI_SLOW_CLK:
1160                 return get_emi_slow_clk();
1161         case MXC_DDR_CLK:
1162                 return get_mmdc_ch0_clk();
1163         case MXC_ESDHC_CLK:
1164                 return get_usdhc_clk(0);
1165         case MXC_ESDHC2_CLK:
1166                 return get_usdhc_clk(1);
1167         case MXC_ESDHC3_CLK:
1168                 return get_usdhc_clk(2);
1169         case MXC_ESDHC4_CLK:
1170                 return get_usdhc_clk(3);
1171         case MXC_SATA_CLK:
1172                 return get_ahb_clk();
1173         default:
1174                 printf("Unsupported MXC CLK: %d\n", clk);
1175                 break;
1176         }
1177
1178         return 0;
1179 }
1180
1181 /*
1182  * Dump some core clockes.
1183  */
1184 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1185 {
1186         u32 freq;
1187         freq = decode_pll(PLL_SYS, MXC_HCLK);
1188         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1189         freq = decode_pll(PLL_BUS, MXC_HCLK);
1190         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
1191         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1192         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
1193         freq = decode_pll(PLL_ENET, MXC_HCLK);
1194         printf("PLL_NET    %8d MHz\n", freq / 1000000);
1195
1196         printf("\n");
1197         printf("ARM        %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
1198         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1199         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1200 #ifdef CONFIG_MXC_SPI
1201         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1202 #endif
1203         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1204         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1205         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1206         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1207         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1208         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1209         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1210         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1211         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1212
1213         return 0;
1214 }
1215
1216 #ifndef CONFIG_MX6SX
1217 void enable_ipu_clock(void)
1218 {
1219         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1220         int reg;
1221         reg = readl(&mxc_ccm->CCGR3);
1222         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1223         writel(reg, &mxc_ccm->CCGR3);
1224
1225         if (is_mx6dqp()) {
1226                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1227                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1228         }
1229 }
1230 #endif
1231
1232 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1233         defined(CONFIG_MX6S)
1234 static void disable_ldb_di_clock_sources(void)
1235 {
1236         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1237         int reg;
1238
1239         /* Make sure PFDs are disabled at boot. */
1240         reg = readl(&mxc_ccm->analog_pfd_528);
1241         /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1242         if (is_mx6sdl())
1243                 reg |= 0x80008080;
1244         else
1245                 reg |= 0x80808080;
1246         writel(reg, &mxc_ccm->analog_pfd_528);
1247
1248         /* Disable PLL3 PFDs */
1249         reg = readl(&mxc_ccm->analog_pfd_480);
1250         reg |= 0x80808080;
1251         writel(reg, &mxc_ccm->analog_pfd_480);
1252
1253         /* Disable PLL5 */
1254         reg = readl(&mxc_ccm->analog_pll_video);
1255         reg &= ~(1 << 13);
1256         writel(reg, &mxc_ccm->analog_pll_video);
1257 }
1258
1259 static void enable_ldb_di_clock_sources(void)
1260 {
1261         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1262         int reg;
1263
1264         reg = readl(&mxc_ccm->analog_pfd_528);
1265         if (is_mx6sdl())
1266                 reg &= ~(0x80008080);
1267         else
1268                 reg &= ~(0x80808080);
1269         writel(reg, &mxc_ccm->analog_pfd_528);
1270
1271         reg = readl(&mxc_ccm->analog_pfd_480);
1272         reg &= ~(0x80808080);
1273         writel(reg, &mxc_ccm->analog_pfd_480);
1274 }
1275
1276 /*
1277  * Try call this function as early in the boot process as possible since the
1278  * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1279  */
1280 void select_ldb_di_clock_source(enum ldb_di_clock clk)
1281 {
1282         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1283         int reg;
1284
1285         /*
1286          * Need to follow a strict procedure when changing the LDB
1287          * clock, else we can introduce a glitch. Things to keep in
1288          * mind:
1289          * 1. The current and new parent clocks must be disabled.
1290          * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1291          * no CG bit.
1292          * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1293          * the top four options are in one mux and the PLL3 option along
1294          * with another option is in the second mux. There is third mux
1295          * used to decide between the first and second mux.
1296          * The code below switches the parent to the bottom mux first
1297          * and then manipulates the top mux. This ensures that no glitch
1298          * will enter the divider.
1299          *
1300          * Need to disable MMDC_CH1 clock manually as there is no CG bit
1301          * for this clock. The only way to disable this clock is to move
1302          * it to pll3_sw_clk and then to disable pll3_sw_clk
1303          * Make sure periph2_clk2_sel is set to pll3_sw_clk
1304          */
1305
1306         /* Disable all ldb_di clock parents */
1307         disable_ldb_di_clock_sources();
1308
1309         /* Set MMDC_CH1 mask bit */
1310         reg = readl(&mxc_ccm->ccdr);
1311         reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1312         writel(reg, &mxc_ccm->ccdr);
1313
1314         /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1315         reg = readl(&mxc_ccm->cbcmr);
1316         reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
1317         writel(reg, &mxc_ccm->cbcmr);
1318
1319         /*
1320          * Set the periph2_clk_sel to the top mux so that
1321          * mmdc_ch1 is from pll3_sw_clk.
1322          */
1323         reg = readl(&mxc_ccm->cbcdr);
1324         reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1325         writel(reg, &mxc_ccm->cbcdr);
1326
1327         /* Wait for the clock switch */
1328         while (readl(&mxc_ccm->cdhipr))
1329                 ;
1330         /* Disable pll3_sw_clk by selecting bypass clock source */
1331         reg = readl(&mxc_ccm->ccsr);
1332         reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1333         writel(reg, &mxc_ccm->ccsr);
1334
1335         /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1336         reg = readl(&mxc_ccm->cs2cdr);
1337         reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1338               | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1339         writel(reg, &mxc_ccm->cs2cdr);
1340
1341         /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1342         reg = readl(&mxc_ccm->cs2cdr);
1343         reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1344               | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1345         reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1346               | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1347         writel(reg, &mxc_ccm->cs2cdr);
1348
1349         /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1350         reg = readl(&mxc_ccm->cs2cdr);
1351         reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1352               | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1353         reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1354               | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1355         writel(reg, &mxc_ccm->cs2cdr);
1356
1357         /* Unbypass pll3_sw_clk */
1358         reg = readl(&mxc_ccm->ccsr);
1359         reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1360         writel(reg, &mxc_ccm->ccsr);
1361
1362         /*
1363          * Set the periph2_clk_sel back to the bottom mux so that
1364          * mmdc_ch1 is from its original parent.
1365          */
1366         reg = readl(&mxc_ccm->cbcdr);
1367         reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1368         writel(reg, &mxc_ccm->cbcdr);
1369
1370         /* Wait for the clock switch */
1371         while (readl(&mxc_ccm->cdhipr))
1372                 ;
1373         /* Clear MMDC_CH1 mask bit */
1374         reg = readl(&mxc_ccm->ccdr);
1375         reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1376         writel(reg, &mxc_ccm->ccdr);
1377
1378         enable_ldb_di_clock_sources();
1379 }
1380 #endif
1381
1382 /***************************************************/
1383
1384 U_BOOT_CMD(
1385         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1386         "display clocks",
1387         ""
1388 );