git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_SYS,        /* System PLL */
  18         PLL_BUS,        /* System Bus PLL*/
  19         PLL_USBOTG,     /* OTG USB PLL */
  20         PLL_ENET,       /* ENET PLL */
  21 };
  22
  23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  24
  25 #ifdef CONFIG_MXC_OCOTP
  26 void enable_ocotp_clk(unsigned char enable)
  27 {
  28         u32 reg;
  29
  30         reg = __raw_readl(&imx_ccm->CCGR2);
  31         if (enable)
  32                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  33         else
  34                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  35         __raw_writel(reg, &imx_ccm->CCGR2);
  36 }
  37 #endif
  38
  39 #ifdef CONFIG_NAND_MXS
  40 void setup_gpmi_io_clk(u32 cfg)
  41 {
  42         /* Disable clocks per ERR007177 from MX6 errata */
  43         clrbits_le32(&imx_ccm->CCGR4,
  44                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  45                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  46                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  47                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  48                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  49
  50         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  51
  52         clrsetbits_le32(&imx_ccm->cs2cdr,
  53                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  54                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  55                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  56                         cfg);
  57
  58         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  59         setbits_le32(&imx_ccm->CCGR4,
  60                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  65 }
  66 #endif
  67
  68 void enable_usboh3_clk(unsigned char enable)
  69 {
  70         u32 reg;
  71
  72         reg = __raw_readl(&imx_ccm->CCGR6);
  73         if (enable)
  74                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  75         else
  76                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  77         __raw_writel(reg, &imx_ccm->CCGR6);
  78
  79 }
  80
  81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  82 void enable_enet_clk(unsigned char enable)
  83 {
  84         u32 mask, *addr;
  85
  86         if (is_cpu_type(MXC_CPU_MX6UL)) {
  87                 mask = MXC_CCM_CCGR3_ENET_MASK;
  88                 addr = &imx_ccm->CCGR3;
  89         } else {
  90                 mask = MXC_CCM_CCGR1_ENET_MASK;
  91                 addr = &imx_ccm->CCGR1;
  92         }
  93
  94         if (enable)
  95                 setbits_le32(addr, mask);
  96         else
  97                 clrbits_le32(addr, mask);
  98 }
  99 #endif
 100
 101 #ifdef CONFIG_MXC_UART
 102 void enable_uart_clk(unsigned char enable)
 103 {
 104         u32 mask;
 105
 106         if (is_cpu_type(MXC_CPU_MX6UL))
 107                 mask = MXC_CCM_CCGR5_UART_MASK;
 108         else
 109                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 110
 111         if (enable)
 112                 setbits_le32(&imx_ccm->CCGR5, mask);
 113         else
 114                 clrbits_le32(&imx_ccm->CCGR5, mask);
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_MMC
 119 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 120 {
 121         u32 mask;
 122
 123         if (bus_num > 3)
 124                 return -EINVAL;
 125
 126         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 127         if (enable)
 128                 setbits_le32(&imx_ccm->CCGR6, mask);
 129         else
 130                 clrbits_le32(&imx_ccm->CCGR6, mask);
 131
 132         return 0;
 133 }
 134 #endif
 135
 136 #ifdef CONFIG_SYS_I2C_MXC
 137 /* i2c_num can be from 0 - 3 */
 138 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 139 {
 140         u32 reg;
 141         u32 mask;
 142         u32 *addr;
 143
 144         if (i2c_num > 3)
 145                 return -EINVAL;
 146         if (i2c_num < 3) {
 147                 mask = MXC_CCM_CCGR_CG_MASK
 148                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 149                         + (i2c_num << 1));
 150                 reg = __raw_readl(&imx_ccm->CCGR2);
 151                 if (enable)
 152                         reg |= mask;
 153                 else
 154                         reg &= ~mask;
 155                 __raw_writel(reg, &imx_ccm->CCGR2);
 156         } else {
 157                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 158                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 159                         addr = &imx_ccm->CCGR6;
 160                 } else {
 161                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 162                         addr = &imx_ccm->CCGR1;
 163                 }
 164                 reg = __raw_readl(addr);
 165                 if (enable)
 166                         reg |= mask;
 167                 else
 168                         reg &= ~mask;
 169                 __raw_writel(reg, addr);
 170         }
 171         return 0;
 172 }
 173 #endif
 174
 175 /* spi_num can be from 0 - SPI_MAX_NUM */
 176 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 177 {
 178         u32 reg;
 179         u32 mask;
 180
 181         if (spi_num > SPI_MAX_NUM)
 182                 return -EINVAL;
 183
 184         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 185         reg = __raw_readl(&imx_ccm->CCGR1);
 186         if (enable)
 187                 reg |= mask;
 188         else
 189                 reg &= ~mask;
 190         __raw_writel(reg, &imx_ccm->CCGR1);
 191         return 0;
 192 }
 193 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 194 {
 195         u32 div;
 196
 197         switch (pll) {
 198         case PLL_SYS:
 199                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 200                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 201
 202                 return (infreq * div) >> 1;
 203         case PLL_BUS:
 204                 div = __raw_readl(&imx_ccm->analog_pll_528);
 205                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 206
 207                 return infreq * (20 + (div << 1));
 208         case PLL_USBOTG:
 209                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 210                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 211
 212                 return infreq * (20 + (div << 1));
 213         case PLL_ENET:
 214                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 215                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 216
 217                 return 25000000 * (div + (div >> 1) + 1);
 218         default:
 219                 return 0;
 220         }
 221         /* NOTREACHED */
 222 }
 223 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 224 {
 225         u32 div;
 226         u64 freq;
 227
 228         switch (pll) {
 229         case PLL_BUS:
 230                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 231                         if (pfd_num == 3) {
 232                                 /* No PFD3 on PPL2 */
 233                                 return 0;
 234                         }
 235                 }
 236                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 237                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 238                 break;
 239         case PLL_USBOTG:
 240                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 241                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 242                 break;
 243         default:
 244                 /* No PFD on other PLL                                       */
 245                 return 0;
 246         }
 247
 248         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 249                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 250 }
 251
 252 static u32 get_mcu_main_clk(void)
 253 {
 254         u32 reg, freq;
 255
 256         reg = __raw_readl(&imx_ccm->cacrr);
 257         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 258         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 259         freq = decode_pll(PLL_SYS, MXC_HCLK);
 260
 261         return freq / (reg + 1);
 262 }
 263
 264 u32 get_periph_clk(void)
 265 {
 266         u32 reg, div = 0, freq = 0;
 267
 268         reg = __raw_readl(&imx_ccm->cbcdr);
 269         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 270                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 271                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 272                 reg = __raw_readl(&imx_ccm->cbcmr);
 273                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 274                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 275
 276                 switch (reg) {
 277                 case 0:
 278                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 279                         break;
 280                 case 1:
 281                 case 2:
 282                         freq = MXC_HCLK;
 283                         break;
 284                 default:
 285                         break;
 286                 }
 287         } else {
 288                 reg = __raw_readl(&imx_ccm->cbcmr);
 289                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 290                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 291
 292                 switch (reg) {
 293                 case 0:
 294                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 295                         break;
 296                 case 1:
 297                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 298                         break;
 299                 case 2:
 300                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 301                         break;
 302                 case 3:
 303                         /* static / 2 divider */
 304                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 305                         break;
 306                 default:
 307                         break;
 308                 }
 309         }
 310
 311         return freq / (div + 1);
 312 }
 313
 314 static u32 get_ipg_clk(void)
 315 {
 316         u32 reg, ipg_podf;
 317
 318         reg = __raw_readl(&imx_ccm->cbcdr);
 319         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 320         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 321
 322         return get_ahb_clk() / (ipg_podf + 1);
 323 }
 324
 325 static u32 get_ipg_per_clk(void)
 326 {
 327         u32 reg, perclk_podf;
 328
 329         reg = __raw_readl(&imx_ccm->cscmr1);
 330         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 331             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 332                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 333                         return MXC_HCLK; /* OSC 24Mhz */
 334         }
 335
 336         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 337
 338         return get_ipg_clk() / (perclk_podf + 1);
 339 }
 340
 341 static u32 get_uart_clk(void)
 342 {
 343         u32 reg, uart_podf;
 344         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 345         reg = __raw_readl(&imx_ccm->cscdr1);
 346
 347         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 348             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 349                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 350                         freq = MXC_HCLK;
 351         }
 352
 353         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 354         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 355
 356         return freq / (uart_podf + 1);
 357 }
 358
 359 static u32 get_cspi_clk(void)
 360 {
 361         u32 reg, cspi_podf;
 362
 363         reg = __raw_readl(&imx_ccm->cscdr2);
 364         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 365                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 366
 367         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 368             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 369                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 370                         return MXC_HCLK / (cspi_podf + 1);
 371         }
 372
 373         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 374 }
 375
 376 static u32 get_axi_clk(void)
 377 {
 378         u32 root_freq, axi_podf;
 379         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 380
 381         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 382         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 383
 384         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 385                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 386                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 387                 else
 388                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 389         } else
 390                 root_freq = get_periph_clk();
 391
 392         return  root_freq / (axi_podf + 1);
 393 }
 394
 395 static u32 get_emi_slow_clk(void)
 396 {
 397         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 398
 399         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 400         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 401         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 402         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 403         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 404
 405         switch (emi_clk_sel) {
 406         case 0:
 407                 root_freq = get_axi_clk();
 408                 break;
 409         case 1:
 410                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 411                 break;
 412         case 2:
 413                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 414                 break;
 415         case 3:
 416                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 417                 break;
 418         }
 419
 420         return root_freq / (emi_slow_podf + 1);
 421 }
 422
 423 static u32 get_mmdc_ch0_clk(void)
 424 {
 425         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 426         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 427
 428         u32 freq, podf, per2_clk2_podf;
 429
 430         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 431             is_cpu_type(MXC_CPU_MX6SL)) {
 432                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 433                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 434                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 435                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 436                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 437                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 438                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 439                                         freq = MXC_HCLK;
 440                                 else
 441                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 442                         } else {
 443                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 444                                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 445                                 else
 446                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 447                         }
 448                 } else {
 449                         per2_clk2_podf = 0;
 450                         switch ((cbcmr &
 451                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 452                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 453                         case 0:
 454                                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 455                                 break;
 456                         case 1:
 457                                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 458                                 break;
 459                         case 2:
 460                                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 461                                 break;
 462                         case 3:
 463                                 /* static / 2 divider */
 464                                 freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 465                                 break;
 466                         }
 467                 }
 468                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 469         } else {
 470                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 471                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 472                 return get_periph_clk() / (podf + 1);
 473         }
 474 }
 475
 476 #ifdef CONFIG_FSL_QSPI
 477 /* qspi_num can be from 0 - 1 */
 478 void enable_qspi_clk(int qspi_num)
 479 {
 480         u32 reg = 0;
 481         /* Enable QuadSPI clock */
 482         switch (qspi_num) {
 483         case 0:
 484                 /* disable the clock gate */
 485                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 486
 487                 /* set 50M  : (50 = 396 / 2 / 4) */
 488                 reg = readl(&imx_ccm->cscmr1);
 489                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 490                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 491                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 492                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 493                 writel(reg, &imx_ccm->cscmr1);
 494
 495                 /* enable the clock gate */
 496                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 497                 break;
 498         case 1:
 499                 /*
 500                  * disable the clock gate
 501                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 502                  * disable both of them.
 503                  */
 504                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 505                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 506
 507                 /* set 50M  : (50 = 396 / 2 / 4) */
 508                 reg = readl(&imx_ccm->cs2cdr);
 509                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 510                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 511                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 512                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 513                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 514                 writel(reg, &imx_ccm->cs2cdr);
 515
 516                 /*enable the clock gate*/
 517                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 518                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 519                 break;
 520         default:
 521                 break;
 522         }
 523 }
 524 #endif
 525
 526 #ifdef CONFIG_FEC_MXC
 527 int enable_fec_anatop_clock(enum enet_freq freq)
 528 {
 529         u32 reg = 0;
 530         s32 timeout = 100000;
 531
 532         struct anatop_regs __iomem *anatop =
 533                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 534
 535         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 536                 return -EINVAL;
 537
 538         reg = readl(&anatop->pll_enet);
 539         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 540         reg |= freq;
 541
 542         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 543             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 544                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 545                 writel(reg, &anatop->pll_enet);
 546                 while (timeout--) {
 547                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 548                                 break;
 549                 }
 550                 if (timeout < 0)
 551                         return -ETIMEDOUT;
 552         }
 553
 554         /* Enable FEC clock */
 555         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 556         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 557         writel(reg, &anatop->pll_enet);
 558
 559 #ifdef CONFIG_MX6SX
 560         /*
 561          * Set enet ahb clock to 200MHz
 562          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 563          */
 564         reg = readl(&imx_ccm->chsccdr);
 565         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 566                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 567                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 568         /* PLL2 PFD2 */
 569         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 570         /* Div = 2*/
 571         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 572         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 573         writel(reg, &imx_ccm->chsccdr);
 574
 575         /* Enable enet system clock */
 576         reg = readl(&imx_ccm->CCGR3);
 577         reg |= MXC_CCM_CCGR3_ENET_MASK;
 578         writel(reg, &imx_ccm->CCGR3);
 579 #endif
 580         return 0;
 581 }
 582 #endif
 583
 584 static u32 get_usdhc_clk(u32 port)
 585 {
 586         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 587         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 588         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 589
 590         switch (port) {
 591         case 0:
 592                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 593                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 594                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 595
 596                 break;
 597         case 1:
 598                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 599                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 600                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 601
 602                 break;
 603         case 2:
 604                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 605                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 606                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 607
 608                 break;
 609         case 3:
 610                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 611                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 612                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 613
 614                 break;
 615         default:
 616                 break;
 617         }
 618
 619         if (clk_sel)
 620                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 621         else
 622                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 623
 624         return root_freq / (usdhc_podf + 1);
 625 }
 626
 627 u32 imx_get_uartclk(void)
 628 {
 629         return get_uart_clk();
 630 }
 631
 632 u32 imx_get_fecclk(void)
 633 {
 634         return mxc_get_clock(MXC_IPG_CLK);
 635 }
 636
 637 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 638 static int enable_enet_pll(uint32_t en)
 639 {
 640         struct mxc_ccm_reg *const imx_ccm
 641                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 642         s32 timeout = 100000;
 643         u32 reg = 0;
 644
 645         /* Enable PLLs */
 646         reg = readl(&imx_ccm->analog_pll_enet);
 647         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 648         writel(reg, &imx_ccm->analog_pll_enet);
 649         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 650         while (timeout--) {
 651                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 652                         break;
 653         }
 654         if (timeout <= 0)
 655                 return -EIO;
 656         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 657         writel(reg, &imx_ccm->analog_pll_enet);
 658         reg |= en;
 659         writel(reg, &imx_ccm->analog_pll_enet);
 660         return 0;
 661 }
 662 #endif
 663
 664 #ifdef CONFIG_CMD_SATA
 665 static void ungate_sata_clock(void)
 666 {
 667         struct mxc_ccm_reg *const imx_ccm =
 668                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 669
 670         /* Enable SATA clock. */
 671         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 672 }
 673
 674 int enable_sata_clock(void)
 675 {
 676         ungate_sata_clock();
 677         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 678 }
 679
 680 void disable_sata_clock(void)
 681 {
 682         struct mxc_ccm_reg *const imx_ccm =
 683                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 684
 685         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 686 }
 687 #endif
 688
 689 #ifdef CONFIG_PCIE_IMX
 690 static void ungate_pcie_clock(void)
 691 {
 692         struct mxc_ccm_reg *const imx_ccm =
 693                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 694
 695         /* Enable PCIe clock. */
 696         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 697 }
 698
 699 int enable_pcie_clock(void)
 700 {
 701         struct anatop_regs *anatop_regs =
 702                 (struct anatop_regs *)ANATOP_BASE_ADDR;
 703         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 704         u32 lvds1_clk_sel;
 705
 706         /*
 707          * Here be dragons!
 708          *
 709          * The register ANATOP_MISC1 is not documented in the Freescale
 710          * MX6RM. The register that is mapped in the ANATOP space and
 711          * marked as ANATOP_MISC1 is actually documented in the PMU section
 712          * of the datasheet as PMU_MISC1.
 713          *
 714          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 715          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 716          * for PCI express link that is clocked from the i.MX6.
 717          */
 718 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 719 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 720 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 721 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 722 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 723
 724         if (is_cpu_type(MXC_CPU_MX6SX))
 725                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 726         else
 727                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 728
 729         clrsetbits_le32(&anatop_regs->ana_misc1,
 730                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 731                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 732                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 733
 734         /* PCIe reference clock sourced from AXI. */
 735         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 736
 737         /* Party time! Ungate the clock to the PCIe. */
 738 #ifdef CONFIG_CMD_SATA
 739         ungate_sata_clock();
 740 #endif
 741         ungate_pcie_clock();
 742
 743         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 744                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 745 }
 746 #endif
 747
 748 #ifdef CONFIG_SECURE_BOOT
 749 void hab_caam_clock_enable(unsigned char enable)
 750 {
 751         u32 reg;
 752
 753         /* CG4 ~ CG6, CAAM clocks */
 754         reg = __raw_readl(&imx_ccm->CCGR0);
 755         if (enable)
 756                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 757                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 758                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 759         else
 760                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 761                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 762                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 763         __raw_writel(reg, &imx_ccm->CCGR0);
 764
 765         /* EMI slow clk */
 766         reg = __raw_readl(&imx_ccm->CCGR6);
 767         if (enable)
 768                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
 769         else
 770                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
 771         __raw_writel(reg, &imx_ccm->CCGR6);
 772 }
 773 #endif
 774
 775 static void enable_pll3(void)
 776 {
 777         struct anatop_regs __iomem *anatop =
 778                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 779
 780         /* make sure pll3 is enabled */
 781         if ((readl(&anatop->usb1_pll_480_ctrl) &
 782                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
 783                 /* enable pll's power */
 784                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
 785                        &anatop->usb1_pll_480_ctrl_set);
 786                 writel(0x80, &anatop->ana_misc2_clr);
 787                 /* wait for pll lock */
 788                 while ((readl(&anatop->usb1_pll_480_ctrl) &
 789                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
 790                         ;
 791                 /* disable bypass */
 792                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
 793                        &anatop->usb1_pll_480_ctrl_clr);
 794                 /* enable pll output */
 795                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
 796                        &anatop->usb1_pll_480_ctrl_set);
 797         }
 798 }
 799
 800 void enable_thermal_clk(void)
 801 {
 802         enable_pll3();
 803 }
 804
 805 unsigned int mxc_get_clock(enum mxc_clock clk)
 806 {
 807         switch (clk) {
 808         case MXC_ARM_CLK:
 809                 return get_mcu_main_clk();
 810         case MXC_PER_CLK:
 811                 return get_periph_clk();
 812         case MXC_AHB_CLK:
 813                 return get_ahb_clk();
 814         case MXC_IPG_CLK:
 815                 return get_ipg_clk();
 816         case MXC_IPG_PERCLK:
 817         case MXC_I2C_CLK:
 818                 return get_ipg_per_clk();
 819         case MXC_UART_CLK:
 820                 return get_uart_clk();
 821         case MXC_CSPI_CLK:
 822                 return get_cspi_clk();
 823         case MXC_AXI_CLK:
 824                 return get_axi_clk();
 825         case MXC_EMI_SLOW_CLK:
 826                 return get_emi_slow_clk();
 827         case MXC_DDR_CLK:
 828                 return get_mmdc_ch0_clk();
 829         case MXC_ESDHC_CLK:
 830                 return get_usdhc_clk(0);
 831         case MXC_ESDHC2_CLK:
 832                 return get_usdhc_clk(1);
 833         case MXC_ESDHC3_CLK:
 834                 return get_usdhc_clk(2);
 835         case MXC_ESDHC4_CLK:
 836                 return get_usdhc_clk(3);
 837         case MXC_SATA_CLK:
 838                 return get_ahb_clk();
 839         default:
 840                 printf("Unsupported MXC CLK: %d\n", clk);
 841                 break;
 842         }
 843
 844         return 0;
 845 }
 846
 847 /*
 848  * Dump some core clockes.
 849  */
 850 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 851 {
 852         u32 freq;
 853         freq = decode_pll(PLL_SYS, MXC_HCLK);
 854         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
 855         freq = decode_pll(PLL_BUS, MXC_HCLK);
 856         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
 857         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 858         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
 859         freq = decode_pll(PLL_ENET, MXC_HCLK);
 860         printf("PLL_NET    %8d MHz\n", freq / 1000000);
 861
 862         printf("\n");
 863         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 864         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 865 #ifdef CONFIG_MXC_SPI
 866         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
 867 #endif
 868         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 869         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
 870         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
 871         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
 872         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
 873         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
 874         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
 875         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
 876         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 877
 878         return 0;
 879 }
 880
 881 #ifndef CONFIG_MX6SX
 882 void enable_ipu_clock(void)
 883 {
 884         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 885         int reg;
 886         reg = readl(&mxc_ccm->CCGR3);
 887         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 888         writel(reg, &mxc_ccm->CCGR3);
 889
 890         if (is_mx6dqp()) {
 891                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
 892                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
 893         }
 894 }
 895 #endif
 896 /***************************************************/
 897
 898 U_BOOT_CMD(
 899         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
 900         "display clocks",
 901         ""
 902 );