2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/errno.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
32 PLL_SYS, /* System PLL */
33 PLL_BUS, /* System Bus PLL*/
34 PLL_USBOTG, /* OTG USB PLL */
35 PLL_ENET, /* ENET PLL */
38 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
40 void enable_usboh3_clk(unsigned char enable)
44 reg = __raw_readl(&imx_ccm->CCGR6);
46 reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
48 reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
49 __raw_writel(reg, &imx_ccm->CCGR6);
53 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
59 div = __raw_readl(&imx_ccm->analog_pll_sys);
60 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
62 return infreq * (div >> 1);
64 div = __raw_readl(&imx_ccm->analog_pll_528);
65 div &= BM_ANADIG_PLL_528_DIV_SELECT;
67 return infreq * (20 + (div << 1));
69 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
70 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
72 return infreq * (20 + (div << 1));
74 div = __raw_readl(&imx_ccm->analog_pll_enet);
75 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
77 return (div == 3 ? 125000000 : 25000000 * (div << 1));
84 static u32 get_mcu_main_clk(void)
88 reg = __raw_readl(&imx_ccm->cacrr);
89 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
90 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
91 freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
93 return freq / (reg + 1);
96 u32 get_periph_clk(void)
100 reg = __raw_readl(&imx_ccm->cbcdr);
101 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
102 reg = __raw_readl(&imx_ccm->cbcmr);
103 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
104 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
108 freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
112 freq = CONFIG_SYS_MX6_HCLK;
118 reg = __raw_readl(&imx_ccm->cbcmr);
119 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
120 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
124 freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
127 freq = PLL2_PFD2_FREQ;
130 freq = PLL2_PFD0_FREQ;
133 freq = PLL2_PFD2_DIV_FREQ;
143 static u32 get_ipg_clk(void)
147 reg = __raw_readl(&imx_ccm->cbcdr);
148 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
149 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
151 return get_ahb_clk() / (ipg_podf + 1);
154 static u32 get_ipg_per_clk(void)
156 u32 reg, perclk_podf;
158 reg = __raw_readl(&imx_ccm->cscmr1);
159 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
161 return get_ipg_clk() / (perclk_podf + 1);
164 static u32 get_uart_clk(void)
168 reg = __raw_readl(&imx_ccm->cscdr1);
169 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
170 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
172 return PLL3_80M / (uart_podf + 1);
175 static u32 get_cspi_clk(void)
179 reg = __raw_readl(&imx_ccm->cscdr2);
180 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
181 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
183 return PLL3_60M / (cspi_podf + 1);
186 static u32 get_axi_clk(void)
188 u32 root_freq, axi_podf;
189 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
191 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
192 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
194 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
195 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
196 root_freq = PLL2_PFD2_FREQ;
198 root_freq = PLL3_PFD1_FREQ;
200 root_freq = get_periph_clk();
202 return root_freq / (axi_podf + 1);
205 static u32 get_emi_slow_clk(void)
207 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
209 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
210 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
211 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
212 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
213 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
215 switch (emi_clk_sel) {
217 root_freq = get_axi_clk();
220 root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
223 root_freq = PLL2_PFD2_FREQ;
226 root_freq = PLL2_PFD0_FREQ;
230 return root_freq / (emi_slow_pof + 1);
233 static u32 get_mmdc_ch0_clk(void)
235 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
236 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
237 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
239 return get_periph_clk() / (mmdc_ch0_podf + 1);
242 static u32 get_usdhc_clk(u32 port)
244 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
245 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
246 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
250 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
251 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
252 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
256 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
257 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
258 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
262 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
263 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
264 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
268 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
269 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
270 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
278 root_freq = PLL2_PFD0_FREQ;
280 root_freq = PLL2_PFD2_FREQ;
282 return root_freq / (usdhc_podf + 1);
285 u32 imx_get_uartclk(void)
287 return get_uart_clk();
290 u32 imx_get_fecclk(void)
292 return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
295 int enable_sata_clock(void)
298 s32 timeout = 100000;
299 struct mxc_ccm_reg *const imx_ccm
300 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
302 /* Enable sata clock */
303 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
304 reg |= MXC_CCM_CCGR5_CG2_MASK;
305 writel(reg, &imx_ccm->CCGR5);
308 reg = readl(&imx_ccm->analog_pll_enet);
309 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
310 writel(reg, &imx_ccm->analog_pll_enet);
311 reg |= BM_ANADIG_PLL_SYS_ENABLE;
313 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
318 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
319 writel(reg, &imx_ccm->analog_pll_enet);
320 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
321 writel(reg, &imx_ccm->analog_pll_enet);
326 unsigned int mxc_get_clock(enum mxc_clock clk)
330 return get_mcu_main_clk();
332 return get_periph_clk();
334 return get_ahb_clk();
336 return get_ipg_clk();
338 return get_ipg_per_clk();
340 return get_uart_clk();
342 return get_cspi_clk();
344 return get_axi_clk();
345 case MXC_EMI_SLOW_CLK:
346 return get_emi_slow_clk();
348 return get_mmdc_ch0_clk();
350 return get_usdhc_clk(0);
352 return get_usdhc_clk(1);
354 return get_usdhc_clk(2);
356 return get_usdhc_clk(3);
358 return get_ahb_clk();
367 * Dump some core clockes.
369 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
372 freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
373 printf("PLL_SYS %8d MHz\n", freq / 1000000);
374 freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
375 printf("PLL_BUS %8d MHz\n", freq / 1000000);
376 freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
377 printf("PLL_OTG %8d MHz\n", freq / 1000000);
378 freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
379 printf("PLL_NET %8d MHz\n", freq / 1000000);
382 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
383 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
384 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
385 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
386 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
387 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
388 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
389 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
390 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
391 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
392 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
393 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
398 /***************************************************/
401 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,