git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_SYS,        /* System PLL */
  18         PLL_BUS,        /* System Bus PLL*/
  19         PLL_USBOTG,     /* OTG USB PLL */
  20         PLL_ENET,       /* ENET PLL */
  21         PLL_AUDIO,      /* AUDIO PLL */
  22         PLL_VIDEO,      /* AUDIO PLL */
  23 };
  24
  25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  26
  27 #ifdef CONFIG_MXC_OCOTP
  28 void enable_ocotp_clk(unsigned char enable)
  29 {
  30         u32 reg;
  31
  32         reg = __raw_readl(&imx_ccm->CCGR2);
  33         if (enable)
  34                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  35         else
  36                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  37         __raw_writel(reg, &imx_ccm->CCGR2);
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_NAND_MXS
  42 void setup_gpmi_io_clk(u32 cfg)
  43 {
  44         /* Disable clocks per ERR007177 from MX6 errata */
  45         clrbits_le32(&imx_ccm->CCGR4,
  46                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  47                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  48                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  49                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  50                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  51
  52 #if defined(CONFIG_MX6SX)
  53         clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  54
  55         clrsetbits_le32(&imx_ccm->cs2cdr,
  56                         MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  57                         MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  58                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  59                         cfg);
  60
  61         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  62 #else
  63         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  64
  65         clrsetbits_le32(&imx_ccm->cs2cdr,
  66                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  67                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  68                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  69                         cfg);
  70
  71         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  72 #endif
  73         setbits_le32(&imx_ccm->CCGR4,
  74                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  77                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  78                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  79 }
  80 #endif
  81
  82 void enable_usboh3_clk(unsigned char enable)
  83 {
  84         u32 reg;
  85
  86         reg = __raw_readl(&imx_ccm->CCGR6);
  87         if (enable)
  88                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  89         else
  90                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  91         __raw_writel(reg, &imx_ccm->CCGR6);
  92
  93 }
  94
  95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  96 void enable_enet_clk(unsigned char enable)
  97 {
  98         u32 mask, *addr;
  99
 100         if (is_cpu_type(MXC_CPU_MX6UL)) {
 101                 mask = MXC_CCM_CCGR3_ENET_MASK;
 102                 addr = &imx_ccm->CCGR3;
 103         } else {
 104                 mask = MXC_CCM_CCGR1_ENET_MASK;
 105                 addr = &imx_ccm->CCGR1;
 106         }
 107
 108         if (enable)
 109                 setbits_le32(addr, mask);
 110         else
 111                 clrbits_le32(addr, mask);
 112 }
 113 #endif
 114
 115 #ifdef CONFIG_MXC_UART
 116 void enable_uart_clk(unsigned char enable)
 117 {
 118         u32 mask;
 119
 120         if (is_cpu_type(MXC_CPU_MX6UL))
 121                 mask = MXC_CCM_CCGR5_UART_MASK;
 122         else
 123                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 124
 125         if (enable)
 126                 setbits_le32(&imx_ccm->CCGR5, mask);
 127         else
 128                 clrbits_le32(&imx_ccm->CCGR5, mask);
 129 }
 130 #endif
 131
 132 #ifdef CONFIG_MMC
 133 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 134 {
 135         u32 mask;
 136
 137         if (bus_num > 3)
 138                 return -EINVAL;
 139
 140         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 141         if (enable)
 142                 setbits_le32(&imx_ccm->CCGR6, mask);
 143         else
 144                 clrbits_le32(&imx_ccm->CCGR6, mask);
 145
 146         return 0;
 147 }
 148 #endif
 149
 150 #ifdef CONFIG_SYS_I2C_MXC
 151 /* i2c_num can be from 0 - 3 */
 152 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 153 {
 154         u32 reg;
 155         u32 mask;
 156         u32 *addr;
 157
 158         if (i2c_num > 3)
 159                 return -EINVAL;
 160         if (i2c_num < 3) {
 161                 mask = MXC_CCM_CCGR_CG_MASK
 162                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 163                         + (i2c_num << 1));
 164                 reg = __raw_readl(&imx_ccm->CCGR2);
 165                 if (enable)
 166                         reg |= mask;
 167                 else
 168                         reg &= ~mask;
 169                 __raw_writel(reg, &imx_ccm->CCGR2);
 170         } else {
 171                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 172                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 173                         addr = &imx_ccm->CCGR6;
 174                 } else {
 175                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 176                         addr = &imx_ccm->CCGR1;
 177                 }
 178                 reg = __raw_readl(addr);
 179                 if (enable)
 180                         reg |= mask;
 181                 else
 182                         reg &= ~mask;
 183                 __raw_writel(reg, addr);
 184         }
 185         return 0;
 186 }
 187 #endif
 188
 189 /* spi_num can be from 0 - SPI_MAX_NUM */
 190 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 191 {
 192         u32 reg;
 193         u32 mask;
 194
 195         if (spi_num > SPI_MAX_NUM)
 196                 return -EINVAL;
 197
 198         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 199         reg = __raw_readl(&imx_ccm->CCGR1);
 200         if (enable)
 201                 reg |= mask;
 202         else
 203                 reg &= ~mask;
 204         __raw_writel(reg, &imx_ccm->CCGR1);
 205         return 0;
 206 }
 207 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 208 {
 209         u32 div, test_div, pll_num, pll_denom;
 210
 211         switch (pll) {
 212         case PLL_SYS:
 213                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 214                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 215
 216                 return (infreq * div) >> 1;
 217         case PLL_BUS:
 218                 div = __raw_readl(&imx_ccm->analog_pll_528);
 219                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 220
 221                 return infreq * (20 + (div << 1));
 222         case PLL_USBOTG:
 223                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 224                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 225
 226                 return infreq * (20 + (div << 1));
 227         case PLL_ENET:
 228                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 229                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 230
 231                 return 25000000 * (div + (div >> 1) + 1);
 232         case PLL_AUDIO:
 233                 div = __raw_readl(&imx_ccm->analog_pll_audio);
 234                 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
 235                         return 0;
 236                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 237                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 238                         return MXC_HCLK;
 239                 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
 240                 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
 241                 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
 242                         BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
 243                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 244                 if (test_div == 3) {
 245                         debug("Error test_div\n");
 246                         return 0;
 247                 }
 248                 test_div = 1 << (2 - test_div);
 249
 250                 return infreq * (div + pll_num / pll_denom) / test_div;
 251         case PLL_VIDEO:
 252                 div = __raw_readl(&imx_ccm->analog_pll_video);
 253                 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
 254                         return 0;
 255                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 256                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 257                         return MXC_HCLK;
 258                 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
 259                 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
 260                 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 261                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 262                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 263                 if (test_div == 3) {
 264                         debug("Error test_div\n");
 265                         return 0;
 266                 }
 267                 test_div = 1 << (2 - test_div);
 268
 269                 return infreq * (div + pll_num / pll_denom) / test_div;
 270         default:
 271                 return 0;
 272         }
 273         /* NOTREACHED */
 274 }
 275 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 276 {
 277         u32 div;
 278         u64 freq;
 279
 280         switch (pll) {
 281         case PLL_BUS:
 282                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 283                         if (pfd_num == 3) {
 284                                 /* No PFD3 on PPL2 */
 285                                 return 0;
 286                         }
 287                 }
 288                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 289                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 290                 break;
 291         case PLL_USBOTG:
 292                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 293                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 294                 break;
 295         default:
 296                 /* No PFD on other PLL                                       */
 297                 return 0;
 298         }
 299
 300         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 301                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 302 }
 303
 304 static u32 get_mcu_main_clk(void)
 305 {
 306         u32 reg, freq;
 307
 308         reg = __raw_readl(&imx_ccm->cacrr);
 309         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 310         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 311         freq = decode_pll(PLL_SYS, MXC_HCLK);
 312
 313         return freq / (reg + 1);
 314 }
 315
 316 u32 get_periph_clk(void)
 317 {
 318         u32 reg, div = 0, freq = 0;
 319
 320         reg = __raw_readl(&imx_ccm->cbcdr);
 321         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 322                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 323                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 324                 reg = __raw_readl(&imx_ccm->cbcmr);
 325                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 326                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 327
 328                 switch (reg) {
 329                 case 0:
 330                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 331                         break;
 332                 case 1:
 333                 case 2:
 334                         freq = MXC_HCLK;
 335                         break;
 336                 default:
 337                         break;
 338                 }
 339         } else {
 340                 reg = __raw_readl(&imx_ccm->cbcmr);
 341                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 342                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 343
 344                 switch (reg) {
 345                 case 0:
 346                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 347                         break;
 348                 case 1:
 349                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 350                         break;
 351                 case 2:
 352                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 353                         break;
 354                 case 3:
 355                         /* static / 2 divider */
 356                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 357                         break;
 358                 default:
 359                         break;
 360                 }
 361         }
 362
 363         return freq / (div + 1);
 364 }
 365
 366 static u32 get_ipg_clk(void)
 367 {
 368         u32 reg, ipg_podf;
 369
 370         reg = __raw_readl(&imx_ccm->cbcdr);
 371         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 372         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 373
 374         return get_ahb_clk() / (ipg_podf + 1);
 375 }
 376
 377 static u32 get_ipg_per_clk(void)
 378 {
 379         u32 reg, perclk_podf;
 380
 381         reg = __raw_readl(&imx_ccm->cscmr1);
 382         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 383             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 384                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 385                         return MXC_HCLK; /* OSC 24Mhz */
 386         }
 387
 388         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 389
 390         return get_ipg_clk() / (perclk_podf + 1);
 391 }
 392
 393 static u32 get_uart_clk(void)
 394 {
 395         u32 reg, uart_podf;
 396         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 397         reg = __raw_readl(&imx_ccm->cscdr1);
 398
 399         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 400             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 401                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 402                         freq = MXC_HCLK;
 403         }
 404
 405         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 406         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 407
 408         return freq / (uart_podf + 1);
 409 }
 410
 411 static u32 get_cspi_clk(void)
 412 {
 413         u32 reg, cspi_podf;
 414
 415         reg = __raw_readl(&imx_ccm->cscdr2);
 416         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 417                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 418
 419         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 420             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 421                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 422                         return MXC_HCLK / (cspi_podf + 1);
 423         }
 424
 425         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 426 }
 427
 428 static u32 get_axi_clk(void)
 429 {
 430         u32 root_freq, axi_podf;
 431         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 432
 433         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 434         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 435
 436         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 437                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 438                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 439                 else
 440                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 441         } else
 442                 root_freq = get_periph_clk();
 443
 444         return  root_freq / (axi_podf + 1);
 445 }
 446
 447 static u32 get_emi_slow_clk(void)
 448 {
 449         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 450
 451         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 452         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 453         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 454         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 455         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 456
 457         switch (emi_clk_sel) {
 458         case 0:
 459                 root_freq = get_axi_clk();
 460                 break;
 461         case 1:
 462                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 463                 break;
 464         case 2:
 465                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 466                 break;
 467         case 3:
 468                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 469                 break;
 470         }
 471
 472         return root_freq / (emi_slow_podf + 1);
 473 }
 474
 475 static u32 get_mmdc_ch0_clk(void)
 476 {
 477         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 478         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 479
 480         u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 481
 482         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 483             is_cpu_type(MXC_CPU_MX6SL)) {
 484                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 485                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 486                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 487                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 488                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 489                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 490                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 491                                         freq = MXC_HCLK;
 492                                 else
 493                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 494                         } else {
 495                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 496                                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 497                                 else
 498                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 499                         }
 500                 } else {
 501                         per2_clk2_podf = 0;
 502                         switch ((cbcmr &
 503                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 504                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 505                         case 0:
 506                                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 507                                 break;
 508                         case 1:
 509                                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 510                                 break;
 511                         case 2:
 512                                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 513                                 break;
 514                         case 3:
 515                                 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
 516                                 switch (pmu_misc2_audio_div) {
 517                                 case 0:
 518                                 case 2:
 519                                         pmu_misc2_audio_div = 1;
 520                                         break;
 521                                 case 1:
 522                                         pmu_misc2_audio_div = 2;
 523                                         break;
 524                                 case 3:
 525                                         pmu_misc2_audio_div = 4;
 526                                         break;
 527                                 }
 528                                 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
 529                                         pmu_misc2_audio_div;
 530                                 break;
 531                         }
 532                 }
 533                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 534         } else {
 535                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 536                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 537                 return get_periph_clk() / (podf + 1);
 538         }
 539 }
 540
 541 #if defined(CONFIG_VIDEO_MXS)
 542 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
 543                             u32 post_div)
 544 {
 545         u32 reg = 0;
 546         ulong start;
 547
 548         debug("pll5 div = %d, num = %d, denom = %d\n",
 549               pll_div, pll_num, pll_denom);
 550
 551         /* Power up PLL5 video */
 552         writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
 553                BM_ANADIG_PLL_VIDEO_BYPASS |
 554                BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 555                BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 556                &imx_ccm->analog_pll_video_clr);
 557
 558         /* Set div, num and denom */
 559         switch (post_div) {
 560         case 1:
 561                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 562                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
 563                        &imx_ccm->analog_pll_video_set);
 564                 break;
 565         case 2:
 566                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 567                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
 568                        &imx_ccm->analog_pll_video_set);
 569                 break;
 570         case 4:
 571                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 572                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
 573                        &imx_ccm->analog_pll_video_set);
 574                 break;
 575         default:
 576                 puts("Wrong test_div!\n");
 577                 return -EINVAL;
 578         }
 579
 580         writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
 581                &imx_ccm->analog_pll_video_num);
 582         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
 583                &imx_ccm->analog_pll_video_denom);
 584
 585         /* Wait PLL5 lock */
 586         start = get_timer(0);   /* Get current timestamp */
 587
 588         do {
 589                 reg = readl(&imx_ccm->analog_pll_video);
 590                 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
 591                         /* Enable PLL out */
 592                         writel(BM_ANADIG_PLL_VIDEO_ENABLE,
 593                                &imx_ccm->analog_pll_video_set);
 594                         return 0;
 595                 }
 596         } while (get_timer(0) < (start + 10)); /* Wait 10ms */
 597
 598         puts("Lock PLL5 timeout\n");
 599
 600         return -ETIME;
 601 }
 602
 603 /*
 604  * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
 605  *
 606  * 'freq' using KHz as unit, see driver/video/mxsfb.c.
 607  */
 608 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 609 {
 610         u32 reg = 0;
 611         u32 hck = MXC_HCLK / 1000;
 612         /* DIV_SELECT ranges from 27 to 54 */
 613         u32 min = hck * 27;
 614         u32 max = hck * 54;
 615         u32 temp, best = 0;
 616         u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
 617         u32 pll_div, pll_num, pll_denom, post_div = 1;
 618
 619         debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 620
 621         if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
 622                 debug("This chip not support lcd!\n");
 623                 return;
 624         }
 625
 626         if (base_addr == LCDIF1_BASE_ADDR) {
 627                 reg = readl(&imx_ccm->cscdr2);
 628                 /* Can't change clocks when clock not from pre-mux */
 629                 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
 630                         return;
 631         }
 632
 633         if (is_cpu_type(MXC_CPU_MX6SX)) {
 634                 reg = readl(&imx_ccm->cscdr2);
 635                 /* Can't change clocks when clock not from pre-mux */
 636                 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
 637                         return;
 638         }
 639
 640         temp = freq * max_pred * max_postd;
 641         if (temp > max) {
 642                 puts("Please decrease freq, too large!\n");
 643                 return;
 644         }
 645         if (temp < min) {
 646                 /*
 647                  * Register: PLL_VIDEO
 648                  * Bit Field: POST_DIV_SELECT
 649                  * 00 — Divide by 4.
 650                  * 01 — Divide by 2.
 651                  * 10 — Divide by 1.
 652                  * 11 — Reserved
 653                  * No need to check post_div(1)
 654                  */
 655                 for (post_div = 2; post_div <= 4; post_div <<= 1) {
 656                         if ((temp * post_div) > min) {
 657                                 freq *= post_div;
 658                                 break;
 659                         }
 660                 }
 661
 662                 if (post_div > 4) {
 663                         printf("Fail to set rate to %dkhz", freq);
 664                         return;
 665                 }
 666         }
 667
 668         /* Choose the best pred and postd to match freq for lcd */
 669         for (i = 1; i <= max_pred; i++) {
 670                 for (j = 1; j <= max_postd; j++) {
 671                         temp = freq * i * j;
 672                         if (temp > max || temp < min)
 673                                 continue;
 674                         if (best == 0 || temp < best) {
 675                                 best = temp;
 676                                 pred = i;
 677                                 postd = j;
 678                         }
 679                 }
 680         }
 681
 682         if (best == 0) {
 683                 printf("Fail to set rate to %dKHz", freq);
 684                 return;
 685         }
 686
 687         debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
 688
 689         pll_div = best / hck;
 690         pll_denom = 1000000;
 691         pll_num = (best - hck * pll_div) * pll_denom / hck;
 692
 693         /*
 694          *                                  pll_num
 695          *             (24MHz * (pll_div + --------- ))
 696          *                                 pll_denom
 697          *freq KHz =  --------------------------------
 698          *             post_div * pred * postd * 1000
 699          */
 700
 701         if (base_addr == LCDIF1_BASE_ADDR) {
 702                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 703                         return;
 704
 705                 /* Select pre-lcd clock to PLL5 and set pre divider */
 706                 clrsetbits_le32(&imx_ccm->cscdr2,
 707                                 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
 708                                 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
 709                                 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
 710                                 ((pred - 1) <<
 711                                  MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
 712
 713                 /* Set the post divider */
 714                 clrsetbits_le32(&imx_ccm->cbcmr,
 715                                 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 716                                 ((postd - 1) <<
 717                                  MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
 718         } else if (is_cpu_type(MXC_CPU_MX6SX)) {
 719                 /* Setting LCDIF2 for i.MX6SX */
 720                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 721                         return;
 722
 723                 /* Select pre-lcd clock to PLL5 and set pre divider */
 724                 clrsetbits_le32(&imx_ccm->cscdr2,
 725                                 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
 726                                 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
 727                                 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
 728                                 ((pred - 1) <<
 729                                  MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
 730
 731                 /* Set the post divider */
 732                 clrsetbits_le32(&imx_ccm->cscmr1,
 733                                 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
 734                                 ((postd - 1) <<
 735                                  MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 736         }
 737 }
 738
 739 int enable_lcdif_clock(u32 base_addr)
 740 {
 741         u32 reg = 0;
 742         u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 743
 744         if (is_cpu_type(MXC_CPU_MX6SX)) {
 745                 if ((base_addr == LCDIF1_BASE_ADDR) ||
 746                     (base_addr == LCDIF2_BASE_ADDR)) {
 747                         puts("Wrong LCD interface!\n");
 748                         return -EINVAL;
 749                 }
 750                 /* Set to pre-mux clock at default */
 751                 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 752                         MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
 753                         MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 754                 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 755                         (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
 756                          MXC_CCM_CCGR3_DISP_AXI_MASK) :
 757                         (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 758                          MXC_CCM_CCGR3_DISP_AXI_MASK);
 759         } else if (is_cpu_type(MXC_CPU_MX6UL)) {
 760                 if (base_addr != LCDIF1_BASE_ADDR) {
 761                         puts("Wrong LCD interface!\n");
 762                         return -EINVAL;
 763                 }
 764                 /* Set to pre-mux clock at default */
 765                 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 766                 lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
 767         } else {
 768                 return 0;
 769         }
 770
 771         reg = readl(&imx_ccm->cscdr2);
 772         reg &= ~lcdif_clk_sel_mask;
 773         writel(reg, &imx_ccm->cscdr2);
 774
 775         /* Enable the LCDIF pix clock */
 776         reg = readl(&imx_ccm->CCGR3);
 777         reg |= lcdif_ccgr3_mask;
 778         writel(reg, &imx_ccm->CCGR3);
 779
 780         reg = readl(&imx_ccm->CCGR2);
 781         reg |= MXC_CCM_CCGR2_LCD_MASK;
 782         writel(reg, &imx_ccm->CCGR2);
 783
 784         return 0;
 785 }
 786 #endif
 787
 788 #ifdef CONFIG_FSL_QSPI
 789 /* qspi_num can be from 0 - 1 */
 790 void enable_qspi_clk(int qspi_num)
 791 {
 792         u32 reg = 0;
 793         /* Enable QuadSPI clock */
 794         switch (qspi_num) {
 795         case 0:
 796                 /* disable the clock gate */
 797                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 798
 799                 /* set 50M  : (50 = 396 / 2 / 4) */
 800                 reg = readl(&imx_ccm->cscmr1);
 801                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 802                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 803                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 804                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 805                 writel(reg, &imx_ccm->cscmr1);
 806
 807                 /* enable the clock gate */
 808                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 809                 break;
 810         case 1:
 811                 /*
 812                  * disable the clock gate
 813                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 814                  * disable both of them.
 815                  */
 816                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 817                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 818
 819                 /* set 50M  : (50 = 396 / 2 / 4) */
 820                 reg = readl(&imx_ccm->cs2cdr);
 821                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 822                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 823                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 824                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 825                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 826                 writel(reg, &imx_ccm->cs2cdr);
 827
 828                 /*enable the clock gate*/
 829                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 830                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 831                 break;
 832         default:
 833                 break;
 834         }
 835 }
 836 #endif
 837
 838 #ifdef CONFIG_FEC_MXC
 839 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 840 {
 841         u32 reg = 0;
 842         s32 timeout = 100000;
 843
 844         struct anatop_regs __iomem *anatop =
 845                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 846
 847         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 848                 return -EINVAL;
 849
 850         reg = readl(&anatop->pll_enet);
 851
 852         if (fec_id == 0) {
 853                 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 854                 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 855         } else if (fec_id == 1) {
 856                 /* Only i.MX6SX/UL support ENET2 */
 857                 if (!(is_cpu_type(MXC_CPU_MX6SX) ||
 858                       is_cpu_type(MXC_CPU_MX6UL)))
 859                         return -EINVAL;
 860                 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 861                 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
 862         } else {
 863                 return -EINVAL;
 864         }
 865
 866         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 867             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 868                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 869                 writel(reg, &anatop->pll_enet);
 870                 while (timeout--) {
 871                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 872                                 break;
 873                 }
 874                 if (timeout < 0)
 875                         return -ETIMEDOUT;
 876         }
 877
 878         /* Enable FEC clock */
 879         if (fec_id == 0)
 880                 reg |= BM_ANADIG_PLL_ENET_ENABLE;
 881         else
 882                 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 883         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 884         writel(reg, &anatop->pll_enet);
 885
 886 #ifdef CONFIG_MX6SX
 887         /*
 888          * Set enet ahb clock to 200MHz
 889          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 890          */
 891         reg = readl(&imx_ccm->chsccdr);
 892         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 893                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 894                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 895         /* PLL2 PFD2 */
 896         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 897         /* Div = 2*/
 898         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 899         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 900         writel(reg, &imx_ccm->chsccdr);
 901
 902         /* Enable enet system clock */
 903         reg = readl(&imx_ccm->CCGR3);
 904         reg |= MXC_CCM_CCGR3_ENET_MASK;
 905         writel(reg, &imx_ccm->CCGR3);
 906 #endif
 907         return 0;
 908 }
 909 #endif
 910
 911 static u32 get_usdhc_clk(u32 port)
 912 {
 913         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 914         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 915         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 916
 917         switch (port) {
 918         case 0:
 919                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 920                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 921                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 922
 923                 break;
 924         case 1:
 925                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 926                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 927                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 928
 929                 break;
 930         case 2:
 931                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 932                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 933                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 934
 935                 break;
 936         case 3:
 937                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 938                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 939                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 940
 941                 break;
 942         default:
 943                 break;
 944         }
 945
 946         if (clk_sel)
 947                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 948         else
 949                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 950
 951         return root_freq / (usdhc_podf + 1);
 952 }
 953
 954 u32 imx_get_uartclk(void)
 955 {
 956         return get_uart_clk();
 957 }
 958
 959 u32 imx_get_fecclk(void)
 960 {
 961         return mxc_get_clock(MXC_IPG_CLK);
 962 }
 963
 964 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 965 static int enable_enet_pll(uint32_t en)
 966 {
 967         struct mxc_ccm_reg *const imx_ccm
 968                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 969         s32 timeout = 100000;
 970         u32 reg = 0;
 971
 972         /* Enable PLLs */
 973         reg = readl(&imx_ccm->analog_pll_enet);
 974         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 975         writel(reg, &imx_ccm->analog_pll_enet);
 976         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 977         while (timeout--) {
 978                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 979                         break;
 980         }
 981         if (timeout <= 0)
 982                 return -EIO;
 983         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 984         writel(reg, &imx_ccm->analog_pll_enet);
 985         reg |= en;
 986         writel(reg, &imx_ccm->analog_pll_enet);
 987         return 0;
 988 }
 989 #endif
 990
 991 #ifdef CONFIG_CMD_SATA
 992 static void ungate_sata_clock(void)
 993 {
 994         struct mxc_ccm_reg *const imx_ccm =
 995                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 996
 997         /* Enable SATA clock. */
 998         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 999 }
1000
1001 int enable_sata_clock(void)
1002 {
1003         ungate_sata_clock();
1004         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1005 }
1006
1007 void disable_sata_clock(void)
1008 {
1009         struct mxc_ccm_reg *const imx_ccm =
1010                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1011
1012         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1013 }
1014 #endif
1015
1016 #ifdef CONFIG_PCIE_IMX
1017 static void ungate_pcie_clock(void)
1018 {
1019         struct mxc_ccm_reg *const imx_ccm =
1020                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1021
1022         /* Enable PCIe clock. */
1023         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1024 }
1025
1026 int enable_pcie_clock(void)
1027 {
1028         struct anatop_regs *anatop_regs =
1029                 (struct anatop_regs *)ANATOP_BASE_ADDR;
1030         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1031         u32 lvds1_clk_sel;
1032
1033         /*
1034          * Here be dragons!
1035          *
1036          * The register ANATOP_MISC1 is not documented in the Freescale
1037          * MX6RM. The register that is mapped in the ANATOP space and
1038          * marked as ANATOP_MISC1 is actually documented in the PMU section
1039          * of the datasheet as PMU_MISC1.
1040          *
1041          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1042          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1043          * for PCI express link that is clocked from the i.MX6.
1044          */
1045 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
1046 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
1047 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
1048 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1049 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1050
1051         if (is_cpu_type(MXC_CPU_MX6SX))
1052                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1053         else
1054                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1055
1056         clrsetbits_le32(&anatop_regs->ana_misc1,
1057                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1058                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1059                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1060
1061         /* PCIe reference clock sourced from AXI. */
1062         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1063
1064         /* Party time! Ungate the clock to the PCIe. */
1065 #ifdef CONFIG_CMD_SATA
1066         ungate_sata_clock();
1067 #endif
1068         ungate_pcie_clock();
1069
1070         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1071                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1072 }
1073 #endif
1074
1075 #ifdef CONFIG_SECURE_BOOT
1076 void hab_caam_clock_enable(unsigned char enable)
1077 {
1078         u32 reg;
1079
1080         /* CG4 ~ CG6, CAAM clocks */
1081         reg = __raw_readl(&imx_ccm->CCGR0);
1082         if (enable)
1083                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1084                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1085                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1086         else
1087                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1088                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1089                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1090         __raw_writel(reg, &imx_ccm->CCGR0);
1091
1092         /* EMI slow clk */
1093         reg = __raw_readl(&imx_ccm->CCGR6);
1094         if (enable)
1095                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1096         else
1097                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1098         __raw_writel(reg, &imx_ccm->CCGR6);
1099 }
1100 #endif
1101
1102 static void enable_pll3(void)
1103 {
1104         struct anatop_regs __iomem *anatop =
1105                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1106
1107         /* make sure pll3 is enabled */
1108         if ((readl(&anatop->usb1_pll_480_ctrl) &
1109                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1110                 /* enable pll's power */
1111                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1112                        &anatop->usb1_pll_480_ctrl_set);
1113                 writel(0x80, &anatop->ana_misc2_clr);
1114                 /* wait for pll lock */
1115                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1116                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1117                         ;
1118                 /* disable bypass */
1119                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1120                        &anatop->usb1_pll_480_ctrl_clr);
1121                 /* enable pll output */
1122                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1123                        &anatop->usb1_pll_480_ctrl_set);
1124         }
1125 }
1126
1127 void enable_thermal_clk(void)
1128 {
1129         enable_pll3();
1130 }
1131
1132 unsigned int mxc_get_clock(enum mxc_clock clk)
1133 {
1134         switch (clk) {
1135         case MXC_ARM_CLK:
1136                 return get_mcu_main_clk();
1137         case MXC_PER_CLK:
1138                 return get_periph_clk();
1139         case MXC_AHB_CLK:
1140                 return get_ahb_clk();
1141         case MXC_IPG_CLK:
1142                 return get_ipg_clk();
1143         case MXC_IPG_PERCLK:
1144         case MXC_I2C_CLK:
1145                 return get_ipg_per_clk();
1146         case MXC_UART_CLK:
1147                 return get_uart_clk();
1148         case MXC_CSPI_CLK:
1149                 return get_cspi_clk();
1150         case MXC_AXI_CLK:
1151                 return get_axi_clk();
1152         case MXC_EMI_SLOW_CLK:
1153                 return get_emi_slow_clk();
1154         case MXC_DDR_CLK:
1155                 return get_mmdc_ch0_clk();
1156         case MXC_ESDHC_CLK:
1157                 return get_usdhc_clk(0);
1158         case MXC_ESDHC2_CLK:
1159                 return get_usdhc_clk(1);
1160         case MXC_ESDHC3_CLK:
1161                 return get_usdhc_clk(2);
1162         case MXC_ESDHC4_CLK:
1163                 return get_usdhc_clk(3);
1164         case MXC_SATA_CLK:
1165                 return get_ahb_clk();
1166         default:
1167                 printf("Unsupported MXC CLK: %d\n", clk);
1168                 break;
1169         }
1170
1171         return 0;
1172 }
1173
1174 /*
1175  * Dump some core clockes.
1176  */
1177 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1178 {
1179         u32 freq;
1180         freq = decode_pll(PLL_SYS, MXC_HCLK);
1181         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1182         freq = decode_pll(PLL_BUS, MXC_HCLK);
1183         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
1184         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1185         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
1186         freq = decode_pll(PLL_ENET, MXC_HCLK);
1187         printf("PLL_NET    %8d MHz\n", freq / 1000000);
1188
1189         printf("\n");
1190         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1191         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1192 #ifdef CONFIG_MXC_SPI
1193         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1194 #endif
1195         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1196         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1197         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1198         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1199         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1200         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1201         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1202         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1203         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1204
1205         return 0;
1206 }
1207
1208 #ifndef CONFIG_MX6SX
1209 void enable_ipu_clock(void)
1210 {
1211         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1212         int reg;
1213         reg = readl(&mxc_ccm->CCGR3);
1214         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1215         writel(reg, &mxc_ccm->CCGR3);
1216
1217         if (is_mx6dqp()) {
1218                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1219                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1220         }
1221 }
1222 #endif
1223 /***************************************************/
1224
1225 U_BOOT_CMD(
1226         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1227         "display clocks",
1228         ""
1229 );